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i table of contents 1 general description............................................................................................................ ..... 1 2 features ....................................................................................................................... ................. 2 2.1 integrated display buffer ...................................................................................................... ... 2 2.2 microcontroller interface...................................................................................................... .... 2 2.3 lcd panel support .............................................................................................................. ..... 2 2.4 display modes .................................................................................................................. ......... 2 2.5 display features ............................................................................................................... ........ 2 2.6 clock source ................................................................................................................... .......... 3 2.7 miscellaneous.................................................................................................................. .......... 3 2.8 package........................................................................................................................ .............. 3 3 ordering information ........................................................................................................... ... 3 4 block diagram .................................................................................................................. ........... 4 4.1 pin arrangement................................................................................................................ .5 4.1.1 100 pin tqfp ................................................................................................................... ... 5 5 pin description ................................................................................................................ ............ 6 5.1 host interface ................................................................................................................. ........... 7 5.2 lcd interface.................................................................................................................. ........... 9 5.3 clock input.................................................................................................................... ........... 10 5.4 miscellaneous.................................................................................................................. ........ 10 5.5 power and ground ............................................................................................................... ... 10 5.6 summary of configuration options ...................................................................................... 10 5.7 host bus interface pin mapping............................................................................................ 11 5.8 lcd interface pin mapping .................................................................................................... 12 5.9 data bus organization .......................................................................................................... .13 6 functional block descriptions ........................................................................................ 14
ii 6.1 mcu interface .................................................................................................................. ........ 14 6.2 control register ............................................................................................................... ....... 14 6.3 display output................................................................................................................. ........ 14 6.4 display buffer................................................................................................................. ......... 14 6.5 pwm clock and cv pulse control......................................................................................... 14 6.6 clock generator ................................................................................................................ ...... 14 7 registers ...................................................................................................................... ............... 15 7.1 register mapping ............................................................................................................... ..... 15 7.2 register descriptions .......................................................................................................... ... 15 7.2.1 read-only configuration registers............................................................................... 15 7.2.2 clock configuration registers ....................................................................................... 16 7.2.3 look-up table registers ................................................................................................ 17 7.2.4 panel configuration registers ....................................................................................... 21 7.2.5 display mode registers .................................................................................................. 31 7.2.6 floating window registers............................................................................................. 36 7.2.7 miscellaneous registers................................................................................................. 41 7.2.8 general io pins registers............................................................................................... 43 7.2.9 pulse width modulation (pwm) clock and contrast voltage (cv) pulse configuration registers........................................................................................................ ......... 46 7.2.10 cursor mode registers ................................................................................................... 49 8 maximum ratings ................................................................................................................ ....... 60 9 dc characteristics ............................................................................................................. .... 61 10 ac characteristics ............................................................................................................. .... 61 10.1 clock timing................................................................................................................... ......... 62 10.1.1 input clocks ................................................................................................................... .. 62 10.1.2 internal clocks ................................................................................................................ .63 10.2 cpu interface timing........................................................................................................... ... 64 10.2.1 generic #1 interface timing............................................................................................ 64 10.2.2 generic #2 interface timing (e.g. isa) ........................................................................... 66 10.2.3 motorola mc68k #1 interface timing (e.g. mc68000) .................................................. 68 10.2.4 motorola dragonball interface timing with dtack# (e.g. mc68ez328/mc68vz328) 70
iii 10.2.5 motorola dragonball interface timing without dtack# (e.g. mc68ez328/mc68vz328) ........................................................................................................... .... 72 10.2.6 hitachi sh-3 interface timing (e.g. sh7709a) .............................................................. 74 10.2.7 hitachi sh-4 interface timing (e.g. sh7751) ................................................................. 76 10.3 lcd power sequencing ......................................................................................................... 78 10.3.1 passive/tft power-on sequence.................................................................................. 78 10.3.2 passive/tft power-off sequence.................................................................................. 79 10.3.3 power saving status ....................................................................................................... 80 10.4 display interface .............................................................................................................. ....... 81 10.4.1 generic stn panel timing.............................................................................................. 82 10.4.2 monochrome 4-bit panel timing.................................................................................... 84 10.4.3 monochrome 8-bit panel timing.................................................................................... 87 10.4.4 color 4-bit panel timing ................................................................................................. 90 10.4.5 color 8-bit panel timing (format stripe) ...................................................................... 93 10.4.6 generic tft panel timing .............................................................................................. 96 10.4.7 9/12/18-bit tft panel timing.......................................................................................... 97 10.4.8 160x160 sharp hr-tft panel timing (e.g. lq031b1ddxx) ...................................... 101 10.4.9 320x240 sharp hr-tft panel timing (e.g. lq039q2ds01) ...................................... 105 11 clocks......................................................................................................................... ................ 107 11.1 clock descriptions ............................................................................................................. .. 107 11.1.1 bclk ........................................................................................................................... .... 107 11.1.2 mclk........................................................................................................................... .... 108 11.1.3 pclk ........................................................................................................................... .... 108 11.1.4 pwmclk......................................................................................................................... 109 11.2 clocks versus functions ..................................................................................................... 109 12 power saving mode.............................................................................................................. .. 110 13 frame rate calculation ..................................................................................................... 110 14 display data formats .......................................................................................................... 1 11 15 look-up table architecture............................................................................................. 112 15.1 monochrome modes ............................................................................................................. 11 2 15.1.1 1 bit-per-pixel monochrome mode............................................................................... 112 15.1.2 2 bit-per-pixel monochrome mode............................................................................... 112
iv 15.1.3 4 bit-per-pixel monochrome mode............................................................................... 113 15.1.4 8 bit-per-pixel monochrome mode............................................................................... 113 15.1.5 16 bit-per-pixel monochrome mode ............................................................................ 113 15.2 color modes .................................................................................................................... ...... 114 15.2.1 1 bit-per-pixel color ...................................................................................................... 114 15.2.2 2 bit-per-pixel color ...................................................................................................... 115 15.2.3 4 bit-per-pixel color ...................................................................................................... 116 15.2.4 8 bit-per-pixel color mode ............................................................................................ 117 15.2.5 16 bit-per-pixel color mode.......................................................................................... 118 16 big-endian bus interface .................................................................................................... 118 16.1 byte swapping bus data...................................................................................................... 118 16.1.1 16 bpp color depth ....................................................................................................... 119 16.1.2 1/2/4/8 bpp color depth ................................................................................................ 119 17 virtual display mode........................................................................................................... . 120 18 display rotate mode............................................................................................................ . 121 18.1 90 display rotate mode ...................................................................................................... 12 1 18.1.1 register programming .................................................................................................. 121 18.2 180 display rotate mode .................................................................................................... 122 18.2.1 register programming .................................................................................................. 122 18.3 270 display rotate mode .................................................................................................... 123 18.3.1 register programming .................................................................................................. 123 19 floating window mode......................................................................................................... 12 4 19.1 with display rotate mode enabled..................................................................................... 125 19.1.1 display rotate mode 90 ............................................................................................... 125 19.1.2 display rotate mode 180 ............................................................................................. 125 19.1.3 display rotate mode 270 ............................................................................................. 126 20 hardware cursor mode ...................................................................................................... 127 20.1 with display rotate mode enabled..................................................................................... 128 20.1.1 display rotate mode 90 ............................................................................................... 128 20.1.2 display rotate mode 180 ............................................................................................. 129 20.1.3 display rotate mode 270 ............................................................................................. 129
v 20.2 pixel format (normal orientation mode) ............................................................................. 129 20.2.1 4/8/16 bit-per-pixel ......................................................................................................... 13 0 20.3 pixel format (90 ? display rotate mode) .............................................................................. 130 20.3.1 4 bit-per-pixel ................................................................................................................ . 130 20.3.2 8 bit-per-pixel ................................................................................................................ . 131 20.3.3 16 bit-per-pixel ............................................................................................................... 131 20.4 pixel format (180 ? display rotate mode) ............................................................................ 132 20.4.1 4 bit-per-pixel ................................................................................................................ . 132 20.4.2 8 bit-per-pixel ................................................................................................................ . 132 20.4.3 16 bit-per-pixel ............................................................................................................... 133 20.5 pixel format (270 ? display rotate mode) ............................................................................ 133 20.5.1 4 bit-per-pixel ................................................................................................................ . 133 20.5.2 8 bit-per-pixel ................................................................................................................ . 134 20.5.3 16 bit-per-pixel ............................................................................................................... 134 21 application examples .......................................................................................................... 1 35 22 appendix ....................................................................................................................... .............. 141 22.1 package mechanical drawing for 100 pins tqfp.............................................................. 141 22.2 register table ................................................................................................................. ...... 142
vi list of figures figure 4-1 : block diagram ..................................................................................................... ...................... 4 figure 4-2 : pinout diagram ? 100 pin tqfp ..................................................................................... .......... 5 figure 7-1 : display data byte/word swap ....................................................................................... ......... 33 figure 7-2 : pwm clock/cv pulse block diagram .................................................................................. ... 46 figure 10-1 : clock input requirements ......................................................................................... ............ 62 figure 10-2 : generic #1 interface timing ...................................................................................... ............ 64 figure 10-3 : generic #2 interface timing ...................................................................................... ............ 66 figure 10-4 : motorola mc68k #1 interface timing............................................................................... ..... 68 figure 10-5 : motorola dragonball interface with dtack# timing ............................................................ 70 figure 10-6 : motorola dragonball interface without dtack# timing ....................................................... 72 figure 10-7 : hitachi sh-3 interface timing.................................................................................... ............ 74 figure 10-8 : hitachi sh-4 interface timing.................................................................................... ............ 76 figure 10-9 : passive/tft power-on sequence timing ............................................................................ 7 8 figure 10-10 : passive/tft power-off sequence timing .......................................................................... 7 9 figure 10-11 : power saving status timing ...................................................................................... ......... 80 figure 10-12 : panel timing parameters ................................................................................................ 81 figure 10-13 : generic stn panel timing ............................................................................................. 83 figure 10-14 : monochrome 4-bit panel timing .................................................................................... 84 figure 10-15 : monochrome 4-bit panel a.c. timing ........................................................................... 85 figure 10-16 : monochrome 8-bit panel timing .................................................................................... 87 figure 10-17 : monochrome 8-bit panel a.c. timing ........................................................................... 88 figure 10-18 : color 4-bit panel timing .................................................................................................. 90 figure 10-19 : color 4-bit panel a.c. timing ......................................................................................... 91 figure 10-20 : color 8-bit panel timing (format stripe) ...................................................................... 93 figure 10-21 : color 8-bit panel a.c. timing (format stripe) .............................................................. 94 figure 10-22 : generic tft panel timing .............................................................................................. 96 figure 10-23 : 12-bit tft panel timing .................................................................................................. 97 figure 10-24 : tft a.c. timing ................................................................................................................ 99 figure 10-25 : 160x160 sharp hr-tft panel horizontal timing ..................................................... 101 figure 10-26 : 160x160 sharp hr-tft panel vertical timing .......................................................... 103 figure 10-27 : 320x240 sharp hr-tft panel horizontal timing ..................................................... 105 figure 10-28 : 320x240 sharp hr-tft panel vertical timing .......................................................... 106 figure 11-1 : clock generator block diagram ..................................................................................... 107 figure 14-1 : 1/2/4/8/16 bit-per-pixel display data memory organization .............................................. 111 figure 15-1 : 1 bit-per-pixel monochrome mode data output path ................................................. 112 figure 15-2 : 2 bit-per-pixel monochrome mode data output path ................................................. 112 figure 15-3 : 4 bit-per-pixel monochrome mode data output path ................................................. 113 figure 15-4 : 8 bit-per-pixel monochrome mode data output path ................................................. 113 figure 15-5 : 1 bit-per-pixel color mode data output path .............................................................. 114 figure 15-6 : 2 bit-per-pixel color mode data output path .............................................................. 115 figure 15-7 : 4 bit-per-pixel color mode data output path .............................................................. 116 figure 15-8 : 8 bit-per-pixel color mode data output path ............................................................... 117 figure 16-1 : byte-swapping for 16 bpp ............................................................................................... 118 figure 16-2 : byte-swapping for 1/2/4/8 bpp ....................................................................................... 119 figure 17-1 : main window inside virtual image area............................................................................ .. 120 figure 18-1 : relationship between the screen image and the image refreshed in 90 display rotate mode. .......................................................................................................................... ....................... 121 figure 18-2 : relationship between the screen image and the image refreshed in 180 display rotate mode. .......................................................................................................................... ....................... 122
vii figure 18-3 : relationship between the screen image and the image refreshed in 270 display rotate mode. .......................................................................................................................... ....................... 123 figure 19-1 : floating window with display rotate mode disabled ................................................. 124 figure 19-2 : floating window with display rotate mode 90 enabled ........................................... 125 figure 19-3 : floating window with display rotate mode 180 enabled ........................................ 125 figure 19-4 : floating window with display rotate mode 270 enabled ........................................ 126 figure 20-1 : display precedence in hardware cursor ............................................................................ 127 figure 20-2 : cursors on the main window ....................................................................................... ........ 128 figure 20-3 : cursors with display rotate mode 90 enabled.................................................................. 128 figure 20-4 : cursors with display rotate mode 180 enabled................................................................ 129 figure 20-5 : cursors with display rotate mode 270 enabled................................................................ 129 figure 21-1: typical system diagram (generic #1 bus) .......................................................................... 1 35 figure 21-2 : typical system diagram (generic #2 bus) ......................................................................... 1 36 figure 21-3 : typical system diagram (mc68k # 1, motorola 16-bit 68000) .......................................... 137 figure 21-4 : typical system diagram (motorola mc68ez328/mc68vz328 ?dragonball? bus) ............. 138 figure 21-5 : typical system diagram (hitachi sh-3 bus)....................................................................... 1 39 figure 21-6 : typical system diagram (hitachi sh-4 bus)....................................................................... 1 40
viii list of tables table 3-1 : ordering information ............................................................................................... .................... 3 table 4-1 : tqfp pin assignment table .......................................................................................... ............ 6 table 5-1 : host interface pin descriptions .................................................................................... .............. 7 table 5-2 : lcd interface pin descriptions .............................................................................................. 9 table 5-3 : clock input pin descriptions....................................................................................... .............. 10 table 5-4 : miscellaneous pin descriptions ..................................................................................... ........... 10 table 5-5 : power and ground pin descriptions .................................................................................. ...... 10 table 5-6 : summary of power-on/reset options .................................................................................. ... 11 table 5-7 : host bus interface pin mapping ..................................................................................... .......... 11 table 5-8 : lcd interface pin mapping.......................................................................................... ............. 12 table 5-9 : data bus organization.............................................................................................. ................ 13 table 5-10 : pin state summary................................................................................................. ................ 13 table 7-1 : mclk divide selection .............................................................................................. ............... 16 table 7-2 : pclk divide selection.............................................................................................. ................ 17 table 7-3 : pclk source selection .............................................................................................. .............. 17 table 7-4 : panel data width selection ......................................................................................... ............. 21 table 7-5 : active panel resolution selection .................................................................................. .......... 22 table 7-6 : lcd panel type selection........................................................................................... ............. 22 table 7-7 : color invert mode options .................................................................................................... 32 table 7-8 : lcd bit-per-pixel selection .................................................................................................. 33 table 7-9 : display rotate mode select options ................................................................................. ....... 34 table 7-10 : 32-bit address x increments for various color depths.......................................................... 38 table 7-11 : 32-bit address y increments for various color depths.......................................................... 39 table 7-12 : 32-bit address x increments for various color depths.......................................................... 40 table 7-13 : 32-bit address y increments for various color depths.......................................................... 41 table 7-14 : pwm clock control................................................................................................. ................ 46 table 7-15 : cv pulse control .................................................................................................. .................. 47 table 7-16 : pwm clock divide select options................................................................................... ....... 47 table 7-17 : cv pulse divide select options .................................................................................... ......... 48 table 7-18 : pwm duty cycle select options ..................................................................................... ....... 49 table 7-19 : x increment mode for various color depths......................................................................... .52 table 7-20 : y increment mode for various color depths......................................................................... .53 table 8-1 : absolute maximum ratings ........................................................................................... ........... 60 table 8-2 : recommended operating conditions ................................................................................... ... 60 table 9-1 : electrical characteristics for iov dd = 3.3v typical.................................................................... 61 table 10-1 : clock input requirements for clki ................................................................................. ....... 62 table 10-2 : clock input requirements for auxclk............................................................................... ... 63 table 10-3 : internal clock requirements ....................................................................................... ........... 63 table 10-4 : generic #1 interface timing ....................................................................................... ............ 65 table 10-5 : generic #2 interface timing ....................................................................................... ............ 67 table 10-6 : motorola mc68k #1 interface timing ................................................................................ ..... 69 table 10-7 : motorola dragonball interface with dtack# timing ............................................................. 71 table 10-8 : motorola dragonball interface without dtack# timing ........................................................ 73 table 10-9 : hitachi sh-3 interface timing..................................................................................... ............ 75 table 10-10 : hitachi sh-4 interface timing.................................................................................... ........... 77 table 10-11 : passive/tft power-on sequence timing ........................................................................... 78 table 10-12 : passive/tft power-off sequence timing ........................................................................... 7 9 table 10-13 : power saving status timing....................................................................................... .......... 80 table 10-14 : panel timing parameter definition and register summary................................................. 81 table 10-15 : monochrome 4-bit panel a.c. timing ............................................................................... ... 86 table 10-16 : monochrome 8-bit panel a.c. timing ............................................................................... ... 89 table 10-17 : color 4-bit panel a.c. timing.................................................................................... ........... 92 table 10-18 : color 8-bit panel a.c. timing (format stripe) .................................................................... .. 95
ix table 10-19 : tft a.c. timing.................................................................................................. ................ 100 table 10-20 : 160x160 sharp hr-tft horizontal timing ........................................................................ 102 table 10-21 : 160x160 sharp hr-tft panel vertical timing .................................................................. 104 table 10-22 : 320x240 sharp hr-tft panel horizontal timing .............................................................. 106 table 10-23 : 320x240 sharp hr-tft panel vertical timing .................................................................. 106 table 11-1 : bclk clock selection.............................................................................................. ............. 107 table 11-2 : mclk clock selection .............................................................................................. ............ 108 table 11-3 : pclk clock selection.............................................................................................. ............. 108 table 11-4 : relationship between mclk and pclk ............................................................................... 1 09 table 11-5 : pwmclk clock selection ................................................................................................ 109 table 11-6 : ssd1905 internal clock requirements ............................................................................... . 109 table 12-1 : power saving mode function summary .............................................................................. 11 0 table 20-1 : indexing scheme for hardware cursor ............................................................................... .. 127 table 22-1 : ssd1905 register table (1 of 2)................................................................................... ....... 142 table 22-2 : ssd1905 register table (2 of 2)................................................................................... ....... 143
solomon systech limited solomon systech limited solomon systech limited solomon systech limited semiconductor technical data this document contains information on a new product. specifications and information herein are subject to change without notice . copyright ? 2002 solomon systech limited rev 1.3 10/2002 ssd1905 advance information lcd graphics controller cmos 1 general description the ssd1905 is a graphics controller with built-in 80kbyte sram display buffer, supporting color and mono lcd. the ssd1905 can support a wide range of active and passive panels, and interface with various cpus. the advanced design, together with integration of memory and timing circuits make a low cost, low power, single chip solution to meet the handheld devices or appliances market needs, such as pocket/palm-size pcs and mobile communication devices. the ssd1905 supports most of the resolutions commonly used in portable applications, and is featured with hardware display rotation, covering different form factor needs. the controller also features virtual display, floating window (variable size overlay window) and two cursors to reduce the software manipulation. the 32-bit internal data path provides high bandwidth display memory for fast screen updates. the ssd1905 also provides the advantage of a single power supply. the ssd1905 features low-latency cpu access, which supports microprocessors without ready/wait# handshaking signals. this controller impartiality to cpu type or operating system makes it an ideal display solution for a wide variety of applications. the ssd1905 is available in a 100 pin tqfp package.
solomon rev 1.3 10/2002 ssd1905 2 2 features 2.1 integrated display buffer ? embedded 80k byte sram display buffer. 2.2 microcontroller interface ? directly interfaces to : generic #1 bus interface with wait# signal generic #2 bus interface with wait# signal motorola mc68k motorola mc68ez328/mc68vz328 dragonball hitachi sh-3 hitachi sh-4 ? 8-bit processor support with ?glue logic?. ? ?fixed? and low-latency cpu access times. ? registers are memory-mapped with dedicated m/r# input to select between memory and register address space. ? the contiguous 80k byte display buffer is directly accessible through the 17-bit address bus. 2.3 lcd panel support ? 4/8-bit monochrome stn interface. ? 4/8-bit color stn interface. ? 9/12/18-bit active matrix tft interface. ? direct support for 18-bit sharp hr-tft interface (160x160, 320x240). 2.4 display modes ? 1/2/4/8/16 bit-per-pixel (bpp) color depths. ? up to 64 gray shades using frame rate control (frc) and dithering on monochrome passive lcd panels. ? up to 256k colors on passive stn panels. ? up to 256k colors on active matrix lcd panels. ? resolution examples : 320x240 at a color depth of 8 bpp 160x160 at a color depth of 16 bpp 160x240 at a color depth of 16 bpp 2.5 display features ? display rotate mode : 90, 180, 270 counter-clockwise hardware rotation of display image. ? virtual display support : displays image larger than the panel size through the use of panning and scrolling. ? floating window mode : displays a variable size window overlaid on background image. ? 2 hardware cursors (for 4/8/16 bpp) : simultaneously displays two cursors overlaid on background image. ? double buffering/multi-pages: provides smooth animation and instantaneous screen updates.
ssd1905 rev 1.3 10/2002 solomon 3 2.6 clock source ? two clock inputs: clki and auxclk. it is possible to use one clock input only. ? bus clock (bclk) is derived from clki, can be internally divided by 2, 3, or 4. ? memory clock (mclk) is derived from bclk. it can be internally divided by 2, 3, or 4. ? pixel clock (pclk) can be derived from clki, auxclk, bclk, or mclk. it can be internally divided by 2, 3, 4, or 8. 2.7 miscellaneous ? hardware/software color invert ? software power saving mode ? general purpose input / output pins available ? single supply operation : 3.0v ? 3.6v 2.8 package ? 100-pin tqfp package 3 ordering information table 3-1 : ordering information ordering part number package form SSD1905QT2 100 tqfp
solomon rev 1.3 10/2002 ssd1905 4 4 block diagram control registers gpio & look up table (lut) control register & gpio display data prefetch unit frc/tft controls & display data format convertion display output memory r/w control display memory with control display buffer (80kb) read/write decode mcu interface mcu interface clock generator internal clocks gpio[6:0] gpo lframe, lline, lshift, lden, ldata[17:0] we0#, we1#, rd/wr#, rd#, bs#,cs#; reset#, m/r # a[16:0] d[15:0] cf[7:0] wait # clki, auxcl k pulse width modulation clock and contrast voltage pulse control lpwmout, lcvout figure 4-1 : block diagram
ssd1905 rev 1.3 10/2002 solomon 5 4.1 pin arrangement 4.1.1 100 pin tqfp 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 vss iovdd lden corevdd lframe lline lshift ldata0 ldata1 ldata2 ldata3 ldata4 ldata5 ldata6 vss iovdd ldata7 ldata8 ldata9 ldata10 ldata11 ldata12 ldata13 ldata14 ldata15 ldata16 ldata17 vss 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 iovdd a uxclk cf7 cf6 cf5 cf4 cf3 cf2 cf1 cf0 testen a 16 a 15 a 14 a 13 a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 vss vss d9 d10 d11 d12 d13 d14 d15 wait # iovdd clki vss reset # rd/wr # we1 # we0 # rd # bs # m/r # cs # a0 a1 a2 a3 corevdd ssd1905 gpo lcvout gpio0 gpio1 gpio2 gpio3 gpio4 gpio5 gpio6 lpwmout iovdd vss d0 d1 d2 d3 d4 d5 d6 d7 d8 iovdd 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 figure 4-2 : pinout diagram ? 100 pin tqfp note corevdd is an internal regulator output pin. 0.1 f capacitor to v ss must be required on each corevdd pin.
solomon rev 1.3 10/2002 ssd1905 6 table 4-1 : tqfp pin assignment table pin # signal name pin # signal name pin # signal name pin # signal name 1 corevdd 26 iovdd 51 corevdd 76 iovdd 2 a3 27 d8 52 lframe 77 auxclk 3 a2 28 d7 53 lline 78 cf7 4 a1 29 d6 54 lshift 79 cf6 5 a0 30 d5 55 ldata0 80 cf5 6 cs# 31 d4 56 ldata 1 81 cf4 7 m/r# 32 d3 57 ldata 2 82 cf3 8 bs# 33 d2 58 ldata 3 83 cf2 9 rd# 34 d1 59 ldata 4 84 cf1 10 we0# 35 d0 60 ldata 5 85 cf0 11 we1# 36 v ss 61 ldata 6 86 testen 12 rd/wr# 37 iovdd 62 v ss 87 a16 13 reset# 38 lpwmout 63 iovdd 88 a15 14 v ss 39 gpio6 64 ldata 7 89 a14 15 clki 40 gpio5 65 ldata 8 90 a13 16 iovdd 41 gpio4 66 ldata 9 91 a12 17 wait# 42 gpio3 67 ldata 10 92 a11 18 d15 43 gpio2 68 ldata 11 93 a10 19 d14 44 gpio1 69 ldata 12 94 a9 20 d13 45 gpio0 70 ldata 13 95 a8 21 d12 46 lcvout 71 ldata 14 96 a7 22 d11 47 gpo 72 ldata 15 97 a6 23 d10 48 lden 73 ldata 16 98 a5 24 d9 49 iovdd 74 ldata 17 99 a4 25 v ss 50 v ss 75 v ss 100 v ss 5 pin description key: i = input o =output io = bi-directional (input / output) p = power pin lis = lvttl schmitt input lb2 = lvttl io buffer (8ma/-8ma at 3.3v) lb3 = lvttl io buffer (12ma/-12ma at 3.3v) lo3 = lvttl output buffer (12ma/-12ma at 3.3v) lt2 = tri-state output buffer (8ma/-8ma at 3.3v) lt3 = tri-state output buffer (12ma/-12ma at 3.3v) hi-z = high impedance note : lvttl is low voltage ttl (see section 9 ?dc characteristics?).
ssd1905 rev 1.3 10/2002 solomon 7 5.1 host interface table 5-1 : host interface pin descriptions pin name type tqfp pin # cell reset# state description a0 i 5 lis 0 this input pin has multiple functions. ? for generic #1, this pin is not used and should be connected to v ss . ? for generic #2, this is an input of system address bit 0 (a0). ? for mc68k #1, this is an input of the lower data strobe (lds#). ? for dragonball, this pin is not used and should be connected to v ss . ? for sh-3/sh-4, this pin is not used and should be connected to vss. see table 5-7 : host bus interface pin mapping for summary. a[16:1] i 2-4, 87- 99 lis 0 system address bus bits 16-1. d[15:0] io 18-24, 27-35 lb2 hi-z input data from the system data bus. ? for generic #1, these pins are connected to d[15:0]. ? for generic #2, these pins are connected to d[15:0]. ? for mc68k #1, these pins are connected to d[15:0]. ? for dragonball, these pins are connected to d[15:0]. ? for sh-3/sh-4, these pins are connected to d[15:0]. see table 5-7 : host bus interface pin mapping for summary. we0# i 10 lis 1 this input pin has multiple functions. ? for generic #1, this is an input of the write enable signal for the lower data byte (we0#). ? for generic #2, this is an input of the write enable signal (we#). ? for mc68k #1, this pin must be tied to iov dd . ? for dragonball, this is an input of the byte enable signal for the d[7:0] data byte (lwe#). ? for sh-3/sh-4, this is input of the write enable signal for data d[7:0]. see table 5-7 : host bus interface pin mapping for summary. we1# i 11 lis 1 this input pin has multiple functions. ? for generic #1, this is an input of the write enable signal for the upper data byte (we1#). ? for generic #2, this is an input of the byte enable signal for the high data byte (bhe#). ? for mc68k #1, this is an input of the upper data strobe (uds#). ? for dragonball, this is an input of the byte enable signal for the d[15:8] data byte (uwe#). ? for sh-3/sh-4, this is input of the write enable signal for data d[15:8]. see table 5-7 : host bus interface pin mapping for summary. cs# i 6 lis 1 chip select input. see table 5-7 : host bus interface pin mapping for summary. m/r# i 7 lis 0 this input pin is used to select the display buffer or internal registers of the ssd1905. m/r# is set high to access the display buffer and low to access the registers. see table 5-7 : host bus interface pin mapping for summary.
solomon rev 1.3 10/2002 ssd1905 8 pin name type tqfp pin # cell reset# state description bs# i 8 lis 1 this input pin has multiple functions. ? for generic #1, this pin must be tied to iov dd . ? for generic #2, this pin must be tied to iov dd . ? for mc68k #1, this is an input of the address strobe (as#). ? for dragonball, this pin must be tied to iov dd . ? for sh-3/sh-4, this is input of the bus start signal (bs#). see table 5-7 : host bus interface pin mapping for summary. rd/wr# i 12 lis 1 this input pin has multiple functions. ? for generic #1, this is an input of the read command for the upper data byte (rd1#). ? for generic #2, this pin must be tied to iov dd . ? for mc68k #1, this is an input of the r/w# signal. ? for dragonball, this pin must be tied to iov dd . ? for sh-3/sh-4, this is input of the rd/wr# signal. the ssd1905 needs this signal for early decode of the bus cycle. see table 5-7 : host bus interface pin mapping for summary. rd# i 9 lis 1 this input pin has multiple functions. ? for generic #1, this is an input of the read command for the lower data byte (rd0#). ? for generic #2, this is an input of the read command (rd#). ? for mc68k #1, this pin must be tied to iov dd . ? for dragonball, this is an input of the output enable (oe#). ? for sh-3/sh-4, this is input of the read signal (rd#). see table 5-7 : host bus interface pin mapping for summary. wait# o 17 lt2 hi-z during a data transfer, this output pin is driven active to force the system to insert wait states. it is driven inactive to indicate the completion of a data transfer. wait# is released to the high impedance state after the data transfer is complete. its active polarity is configurable. a pull-up or pull-down resistor should be used to resolve any data contention issues. see table 5-6 : summary of power-on/reset options. ? for generic #1, this pin outputs the wait signal (wait#). ? for generic #2, this pin outputs the wait signal (wait#). ? for mc68k #1, this pin outputs the data transfer acknowledge signal (dtack#). ? for dragonball, this pin outputs the data transfer acknowledge signal (dtack#). ? for sh-3 mode, this pin outputs the wait request signal (wait#). ? for sh-4 mode, this pin outputs the device ready signal (rdy#). see table 5-7 : host bus interface pin mapping for summary. reset# i 13 lis 0 active low input to set all internal registers to the default state and to force all signals to their inactive states. it is recommended to place a 0.1 f capacitor to v ss . note : when reset state is released (reset# = ?h?), normal operation can be started after 3 bclk period.
ssd1905 rev 1.3 10/2002 solomon 9 5.2 lcd interface table 5-2 : lcd interface pin descriptions pin name type tqfp pin # cell reset# state description ldata[17:0] o 55-61, 64-74 lo3 0 panel data bits 17-0. lframe o 52 lo3 0 this output pin has multiple functions. ? frame pulse ? sps for sharp hr-tft see table 5-8 : lcd interface pin mapping for summary. lline o 53 lo3 0 this output pin has multiple functions. ? line pulse ? lp for sharp hr-tft see table 5-8 : lcd interface pin mapping for summary. lshift o 54 lo3 0 this output pin has multiple functions. ? shift clock ? clk for sharp hr-tft see table 5-8 : lcd interface pin mapping for summary. lden o 48 lo3 0 this output pin has multiple functions. ? display enable (lden) for tft panels ? lcd backplane bias signal (mod) for all other lcd panels see table 5-8 : lcd interface pin mapping for summary. gpio0 io 45 lis/ lt3 0 this pin has multiple functions. ? ps for sharp hr-tft ? general purpose io pin 0 (gpio0) ? hardware color invert see table 5-8 : lcd interface pin mapping for summary. gpio1 io 44 lb3 0 this pin has multiple functions. ? cls for sharp hr-tft ? general purpose io pin 1 (gpio1) see table 5-8 : lcd interface pin mapping for summary. gpio2 io 43 lb3 0 this pin has multiple functions. ? rev for sharp hr-tft ? general purpose io pin 2 (gpio2) see table 5-8 : lcd interface pin mapping for summary. gpio3 io 42 lb3 0 this pin has multiple functions. ? spl for sharp hr-tft ? general purpose io pin 3 (gpio3) see table 5-8 : lcd interface pin mapping for summary. gpio4 io 41 lb3 0 this pin has multiple functions. ? general purpose io pin 4 (gpio4) see table 5-8 : lcd interface pin mapping for summary. gpio5 io 40 lb3 0 this pin has multiple functions. ? general purpose io pin 5 (gpio5) see table 5-8 : lcd interface pin mapping for summary. gpio6 io 39 lb3 0 this pin has multiple functions. ? general purpose io pin 6 (gpio6) see table 5-8 : lcd interface pin mapping for summary. lpwmout o 38 lb3 0 this output pin has multiple functions. ? pwm clock output ? general purpose output lcvout o 46 lb3 0 this output pin has multiple functions. ? cv pulse output ? general purpose output
solomon rev 1.3 10/2002 ssd1905 10 5.3 clock input table 5-3 : clock input pin descriptions pin name type tqfp pin # cell reset# state description clki i 15 lis ? typically used as input clock source for bus clock and memory clock auxclk i 77 lis ? this pin may be used as input clock source for pixel clock. this input pin must be connected to v ss if not used. 5.4 miscellaneous table 5-4 : miscellaneous pin descriptions pin name type tqfp pin # cell reset # state description cf[7:0] i 78-85 lis ? these inputs are used to configure the ssd1905 ? see table 5-6 : summary of power-on/reset options. note: these pins are used for configuration of the ssd1905 and must be connected directly to iov dd or v ss . gpo o 47 lo3 0 general purpose output (possibly used for controlling the lcd power). testen i 86 lis ? test enable input used for production test only and should be tied to v ss . 5.5 power and ground table 5-5 : power and ground pin descriptions pin name type tqfp pin # cell reset # state description iov dd p 16, 26, 37, 49, 63, 76 p ? power supply pins. it is recommended to place a 0.1 f bypass capacitor close to each of these pins. corev dd p 1, 51 p ? corev dd pins are internal voltage regulator output pins that is used by the internal circuitry only. they cannot be used for driving external circuitry. it is required to place a 0.1 f bypass capacitor close to each of these pins. v ss p 14, 25, 36, 50, 62, 75, 100 p ? ground pins 5.6 summary of configuration options these pins are used for configuration of the ssd1905 and must be connected directly to iov dd or v ss . the state of cf[5:0] is latched on the rising edge of reset# or after the software reset function is activated (reg[a2h] bit 0). changing state at any other time has no effect.
ssd1905 rev 1.3 10/2002 solomon 11 table 5-6 : summary of power-on/reset options power-on/reset state ssd1905 configuration input 1 (connected to iov dd ) 0 (connected to v ss ) cf[2:0] select host bus interface as follows: cf2 cf1 cf0 host bus 0 0 0 sh-3/sh-4 0 0 1 mc68k #1 0 1 0 reserved 0 1 1 generic#1 1 0 0 generic#2 1 0 1 reserved 1 1 0 dragonball (mc68ez328/mc68vz328) 1 1 1 reserved note: the host bus interface is 16-bit only. cf3 configure gpio pins as inputs at power-on configure gpio pins as outputs at power-on (for use by hr-tft when selected) cf4 big endian bus interface little endian bus interface cf5 wait# is active high wait# is active low cf[7:6] clki to bclk divide select: cf7 cf6 clki to bclk divide ratio 0 0 1:1 0 1 2:1 1 0 3:1 1 1 4:1 5.7 host bus interface pin mapping table 5-7 : host bus interface pin mapping ssd1905 pin name generic #1 generic #2 motorola mc68k #1 motorola mc68ez328/ mc68vz328 dragonball hitachi sh-3 hitachi sh-4 a0 connected to v ss a0 lds# connected to v ss connected to vss connected to vss a[16:1] a[16:1] a[16:1] a[16:1] a[16:1] a[16:1] a[16:1] d[15:0] d[15:0] d[15:0] d[15:0] 1 d[15:0] d[15:0] d[15:0] cs# external decode csx# csn# csn# m/r# external decode clki busclk busclk clk clko ckio ckio bs# connected to iov dd as# connected to iov dd bs# bs# rd/wr# rd1# connected to iov dd r/w# connected to iov dd rd/wr# rd/wr# rd# rd0# rd# connected to iov dd oe# rd# rd# we0# we0# we# connected to iov dd lwe# we0# we0# we1# we1# bhe# uds# uwe# we1# we1# wait# wait# wait# dtack# dtack# wait# rdy# reset# reset# reset# reset# reset# reset# reset# note 1 if the target mc68k bus is 32-bit, then these signals should be connected to d[31:16].
solomon rev 1.3 10/2002 ssd1905 12 5.8 lcd interface pin mapping table 5-8 : lcd interface pin mapping pin name monochrome passive panel color passive panel color tft panel 4-bit 8-bit 4-bit 8-bit 9-bit 12-bit 18-bit 18-bit sharp (format stripe) hr-tft 1 lframe lframe sps lline lline lp lshift lshift clk lden mod lden no connect ldata0 drive 0 d0 drive 0 d0(g3) 2 r2 r3 r5 r5 ldata1 drive 0 d1 drive 0 d1(r3) 2 r1 r2 r4 r4 ldata2 drive 0 d2 drive 0 d2(b2) 2 r0 r1 r3 r3 ldata3 drive 0 d3 drive 0 d3(g2) 2 g2 g3 g5 g5 ldata4 d0 d4 d0(r2) 2 d4(r2) 2 g1 g2 g4 g4 ldata5 d1 d5 d1(b1) 2 d5(b1) 2 g0 g1 g3 g3 ldata6 d2 d6 d2(g1) 2 d6(g1) 2 b2 b3 b5 b5 ldata7 d3 d7 d3(r1) 2 d7(r1) 2 b1 b2 b4 b4 ldata8 drive 0 drive 0 drive 0 drive 0 b0 b1 b3 b3 ldata9 drive 0 drive 0 drive 0 drive 0 drive 0 r0 r2 r2 ldata10 drive 0 drive 0 drive 0 drive 0 drive 0 drive 0 r1 r1 ldata11 drive 0 drive 0 drive 0 drive 0 drive 0 drive 0 r0 r0 ldata12 drive 0 drive 0 drive 0 drive 0 drive 0 g0 g2 g2 ldata13 drive 0 drive 0 drive 0 drive 0 drive 0 drive 0 g1 g1 ldata14 drive 0 drive 0 drive 0 drive 0 drive 0 drive 0 g0 g0 ldata15 drive 0 drive 0 drive 0 drive 0 drive 0 b0 b2 b2 ldata16 drive 0 drive 0 drive 0 drive 0 drive 0 drive 0 b1 b1 ldata17 drive 0 drive 0 drive 0 drive 0 drive 0 drive 0 b0 b0 gpio0 gpio0 gpio0 gpio0 gpio0 gpio0 gpio0 gpio0 ps gpio1 gpio1 gpio1 gpio1 gpio1 gpio1 gpio1 gpio1 cls gpio2 gpio2 gpio2 gpio2 gpio2 gpio2 gpio2 gpio2 rev gpio3 gpio3 gpio3 gpio3 gpio3 gpio3 gpio3 gpio3 spl gpio4 gpio4 gpio4 gpio4 gpio4 gpio4 gpio4 gpio4 gpio4 (output only) gpio5 gpio5 gpio5 gpio5 gpio5 gpio5 gpio5 gpio5 gpio5 (output only) gpio6 gpio6 gpio6 gpio6 gpio6 gpio6 gpio6 gpio6 gpio6 (output only) gpo gpo (general purpose output) lcvout lcvout lpwmout lpwmout note 1 gpio pins must be configured as outputs (cf3 = 0 during reset# active) when hr-tft panels are selected. 2 these pin mappings use signal names commonly used for each panel type, however signal names may differ between panel manufacturers. the values shown in brackets represent the color components as mapped to the corresponding ldataxx signals at the first valid edge of lshift. for further ldataxx to lcd interface mapping, see section 10.4 ?display interface?.
ssd1905 rev 1.3 10/2002 solomon 13 5.9 data bus organization there are two data bus architectures, little endian and big endian. little endian means the bytes at lower addresses have lower significance. big endian means the most significant byte has the lowest address. table 5-9 : data bus organization d[15:8] d[7:0] big endian 2n 2n + 1 little endian 2n + 1 2n n : byte address table 5-10 : pin state summary mcu mode (endian) a0 rd/wr# rd# we1# we0# operation x 0 0 1 1 word read x 0 1 1 1 high byte read 2n x 1 0 1 1 low byte read 2n+1 x 1 1 0 0 word write x 1 1 0 1 high byte write 2n generic#1 (big) x 1 1 1 0 low byte write 2n+1 x 0 0 1 1 word read x 0 1 1 1 high byte read 2n+1 x 1 0 1 1 low byte read 2n x 1 1 0 0 word write x 1 1 0 1 high byte write 2n+1 generic#1 (little) x 1 1 1 0 low byte write 2n 0 x 0 0 1 word read 0 x 0 1 1 high byte read 2n 1 x 0 0 1 low byte read 2n+1 0 x 1 0 0 word write 0 x 1 1 0 high byte write 2n generic#2 (big) 1 x 1 0 0 low byte write 2n+1 0 x 0 0 1 word read 1 x 0 0 1 high byte read 2n+1 0 x 0 1 1 low byte read 2n 0 x 1 0 0 word write 1 x 1 0 0 high byte write 2n+1 generic#2 (little) 0 x 1 1 0 low byte write 2n 0 1 x 0 x word read 1 1 x 0 x high byte read 2n 0 1 x 1 x low byte read 2n+1 0 0 x 0 x word write 1 0 x 0 x high byte write 2n mc68k#1 (big) 0 0 x 1 x low byte write 2n+1 0 1 x 0 x word read 0 1 x 1 x high byte read 2n+1 1 1 x 0 x low byte read 2n 0 0 x 0 x word write 0 0 x 1 x high byte write 2n+1 mc68k#1 (little) 1 0 x 0 x low byte write 2n
solomon rev 1.3 10/2002 ssd1905 14 mcu mode (endian) a0 rd/wr# rd# we1# we0# operation x x 0 x x word read x x 1 0 0 word write x x 1 0 1 high byte write 2n mc68ez328 / mc68vz328 (big) x x 1 1 0 low byte write 2n+1 x x 0 x x word read x x 1 0 0 word write x x 1 0 1 high byte write 2n+1 mc68ez328 / mc68vz328 (little) x x 1 1 0 low byte write 2n x x 0 1 1 word read x x 1 0 0 word write x x 1 0 1 high byte write 2n sh-3/sh-4 (big) x x 1 1 0 low byte write 2n+1 x x 0 1 1 word read x x 1 0 0 word write x x 1 0 1 high byte write 2n+1 sh-3/sh-4 (little) x x 1 1 0 low byte write 2n 6 functional block descriptions 6.1 mcu interface responds to bus request for various kinds of mcu and translates to internal interface signals. 6.2 control register the control register stores register data to control the lcd panel. the register data is through the mcu interface read/write to control the register value. the read/write access of lut is also controlled by the control register. the detail of this register and register mapping will be discussed in section 7 ?registers?. 6.3 display output display output serializes the display data from display buffer and reconstructs the data according to the display panel format. when the display mode is not 16 bpp, display data will be converted to color data by the built-in 18 bit lut. for details about lut, please refer to section 15 ?look-up table architecture?. 6.4 display buffer display buffer consists of 80kb sram, which is organized as a 32-bit wide internal data path for fast display data retrieval. 6.5 pwm clock and cv pulse control provides programmable waveform for pulse width modulation (pwm) and contrast voltage (cv) generation. 6.6 clock generator clock generator provides internal clocks. for detail operation of clock generator, please refer to section 11 ?clocks?.
ssd1905 rev 1.3 10/2002 solomon 15 7 registers this section discusses how and where to access the ssd1905 registers. it also provides detailed information about the layout and usage of each register. 7.1 register mapping the ssd1905 registers are memory-mapped. when the system decodes the input pins as cs# = 0 and m/r# = 0, the registers may be accessed. the register space is decoded by a[16:0]. 7.2 register descriptions unless specified otherwise, all register bits are set to 0 during power-on or software reset (reg[a2h] bit 0 = 1). all bits marked ?0? should be programmed as zero. all bits marked ?1? should be programmed as one. key : ro : read only wo : write only rw : read / write na : not applicable x : don?t care 7.2.1 read-only configuration registers display buffer size register reg[01h] bit 7 6 5 4 3 2 1 0 display buffer size bit 7 display buffer size bit 6 display buffer size bit 5 display buffer size bit 4 display buffer size bit 3 display buffer size bit 2 display buffer size bit 1 display buffer size bit 0 type ro ro ro ro ro ro ro ro reset state 0 0 0 1 0 1 0 0 bits 7-0 display buffer size bits [7:0] this register indicates the size of the sram display buffer in 4k byte multiple. the ssd1905 display buffer is 80k bytes and therefore this register returns a value of 20 (14h). value of this register = display buffer size 4k bytes = 80k bytes 4k bytes = 20 (14h) configuration readback register reg[02h] bit 7 6 5 4 3 2 1 0 cf7 status cf6 status cf5 status cf4 status cf3 status cf2 status cf1 status cf0 status type ro ro ro ro ro ro ro ro reset state x x x x x x x x bits 7-0 cf[7:0] status these status bits return the status of the configuration pins cf[7:0]. cf[5:0] are latched at the rising edge of reset# or software reset (reg[a2h] bit 0 = 1).
solomon rev 1.3 10/2002 ssd1905 16 product / revision code register reg[03h] bit 7 6 5 4 3 2 1 0 product code bit 5 product code bit 4 product code bit 3 product code bit 2 product code bit 1 product code bit 0 revision code bit 1 revision code bit 0 type ro ro ro ro ro ro ro ro reset state 0 0 0 1 0 1 x x bits 7-2 product code bits [5:0] these bits indicate the product code. the product code of ssd1905 is 000101. bits 1-0 revision code bits [1:0] these are read-only bits that indicate the revision code. 7.2.2 clock configuration registers memory clock configuration register reg[04h] bit 7 6 5 4 3 2 1 0 0 0 mclk divide select bit 1 mclk divide select bit 0 0 0 0 0 type na na rw rw na na na na reset state 0 0 0 0 0 0 0 0 bits 5-4 mclk divide select bits [1:0] these bits determine the divide used to generate the memory clock (mclk) from the bus clock (bclk). table 7-1 : mclk divide selection mclk divide select bits [1:0] bclk to mclk frequency ratio 00 1:1 01 2:1 10 3:1 11 4:1 pixel clock configuration register reg[05h] bit 7 6 5 4 3 2 1 0 0 pclk divide select bit 2 pclk divide select bit 1 pclk divide select bit 0 0 0 pclk source select bit 1 pclk source select bit 0 type na rw rw rw na na rw rw reset state 0 0 0 0 0 0 0 0 bits 6-4 pclk divide select bits [2:0] these bits determine the divided used to generate the pixel clock (pclk) from the pixel clock source.
ssd1905 rev 1.3 10/2002 solomon 17 table 7-2 : pclk divide selection pclk divide select bits [2:0] pclk source to pclk frequency ratio 000 1:1 001 2:1 010 3:1 011 4:1 1xx 8:1 x = don?t care bits 1-0 pclk source select bits [1:0] these bits determine the source of the pixel clock (pclk). table 7-3 : pclk source selection pclk source select bits [1:0] pclk source 00 mclk 01 bclk 10 clki 11 auxclk 7.2.3 look-up table registers look-up table blue write data register reg[08h] bit 7 6 5 4 3 2 1 0 lut blue write data bit 5 lut blue write data bit 4 lut blue write data bit 3 lut blue write data bit 2 lut blue write data bit 1 lut blue write data bit 0 x x type wo wo wo wo wo wo wo wo reset state 0 0 0 0 0 0 0 0 bits 7-2 lut blue write data bits [5:0] this register contains the data to be written to the blue component of the look-up table. the data is stored in this register until a write to the lut write address register (reg[0bh]) moves the data into the look-up table. note the lut entry is updated only when the lut write address register (reg[0bh]) is written.
solomon rev 1.3 10/2002 ssd1905 18 look-up table green write data register reg[09h] bit 7 6 5 4 3 2 1 0 lut green write data bit 5 lut green write data bit 4 lut green write data bit 3 lut green write data bit 2 lut green write data bit 1 lut green write data bit 0 x x type wo wo wo wo wo wo wo wo reset state 0 0 0 0 0 0 0 0 bits 7-2 lut green write data bits [5:0] this register contains the data to be written to the green component of the look-up table. the data is stored in this register until a write to the lut write address register (reg[0bh]) moves the data into the look-up table. note the lut entry is updated only when the lut write address register (reg[0bh]) is written. look-up table red write data register reg[0ah] bit 7 6 5 4 3 2 1 0 lut red write data bit 5 lut red write data bit 4 lut red write data bit 3 lut red write data bit 2 lut red write data bit 1 lut red write data bit 0 x x type wo wo wo wo wo wo wo wo reset state 0 0 0 0 0 0 0 0 bits 7-2 lut red write data bits [5:0] this register contains the data to be written to the red component of the look-up table. the data is stored in this register until a write to the lut write address register (reg[0bh]) moves the data into the look-up table. note the lut entry is updated only when the lut write address register (reg[0bh]) is written.
ssd1905 rev 1.3 10/2002 solomon 19 look-up table write address register reg[0bh] bit 7 6 5 4 3 2 1 0 lut write address bit 7 lut write address bit 6 lut write address bit 5 lut write address bit 4 lut write address bit 3 lut write address bit 2 lut write address bit 1 lut write address bit 0 type wo wo wo wo wo wo wo wo reset state 0 0 0 0 0 0 0 0 bits 7-0 lut write address bits [7:0] this register is a pointer to the look-up table (lut) which is used to write lut data stored in reg[08h], reg[09h], and reg[0ah]. the data is updated to the lut only with the completion of a write to this register . this is a write-only register and returns 00h if read. note the ssd1905 has three 256-entry, 6-bit-wide luts, one for each of red, green and blue (see section 15 ?look-up table architecture?). look-up table blue read data register reg[0ch] bit 7 6 5 4 3 2 1 0 lut blue read data bit 5 lut blue read data bit 4 lut blue read data bit 3 lut blue read data bit 2 lut blue read data bit 1 lut blue read data bit 0 0 0 type ro ro ro ro ro ro ro ro reset state 0 0 0 0 0 0 0 0 bits 7-2 lut blue read data bits [5:0] this register contains the data from the blue component of the look-up table. the lut entry read is controlled by the lut read address register (reg[0fh]). note this register is updated only when the lut read address register (reg[0fh]) is written. look-up table green read data register reg[0dh] bit 7 6 5 4 3 2 1 0 lut green read data bit 5 lut green read data bit 4 lut green read data bit 3 lut green read data bit 2 lut green read data bit 1 lut green read data bit 0 0 0 type ro ro ro ro ro ro ro ro reset state 0 0 0 0 0 0 0 0 bits 7-2 lut green read data bits [5:0] this register contains the data from the green component of the look-up table. the lut entry read is controlled by the lut read address register (reg[0fh]). note this register is updated only when the lut read address register (reg[0fh]) is written.
solomon rev 1.3 10/2002 ssd1905 20 look-up table red read data register reg[0eh] bit 7 6 5 4 3 2 1 0 lut red read data bit 5 lut red read data bit 4 lut red read data bit 3 lut red read data bit 2 lut red read data bit 1 lut red read data bit 0 0 0 type ro ro ro ro ro ro ro ro reset state 0 0 0 0 0 0 0 0 bits 7-2 lut red read data bits [5:0] this register contains the data from the red component of the look-up table. the lut entry read is controlled by the lut read address register (reg[0fh]). note this register is updated only when the lut read address register (reg[0fh]) is written. look-up table read address register reg[0fh] bit 7 6 5 4 3 2 1 0 lut read address bit 7 lut read address bit 6 lut read address bit 5 lut read address bit 4 lut read address bit 3 lut read address bit 2 lut read address bit 1 lut read address bit 0 type wo wo wo wo wo wo wo wo reset state 0 0 0 0 0 0 0 0 bits 7-0 lut read address bits [7:0] this register is a pointer to the look-up table (lut) which is used to read lut data and store it in reg[0ch], reg[0dh], reg[0eh]. the data is read from the lut only when a write to this register is completed . this is a write-only register and returns 00h if read. note the ssd1905 has three 256-entry, 6-bit-wide luts, one for each of red, green and blue (see section 15 ?look-up table architecture?).
ssd1905 rev 1.3 10/2002 solomon 21 7.2.4 panel configuration registers panel type register reg[10h] bit 7 6 5 4 3 2 1 0 color stn panel select color/mono panel select panel data width bit 1 panel data width bit 0 active panel resolution select 0 panel type bit 1 panel type bit 0 type rw rw rw rw rw na rw rw reset state 0 0 0 0 0 0 0 0 bit 7 color stn panel select when this bit = 0, non color stn lcd panel is selected. when this bit = 1, color stn lcd panel is selected. bit 6 color/mono panel select when this bit = 0, monochrome lcd panel is selected. when this bit = 1, color lcd panel is selected. bits 5-4 panel data width bits [1:0] these bits are determined by the data width of the lcd panel. refer to table 7-4 : panel data width selection for the selection. table 7-4 : panel data width selection panel data width bits [1:0] passive panel data width active panel data width 00 4-bit 9-bit 01 8-bit 12-bit 10 reserved 18-bit 11 reserved reserved bit 3 active panel resolution select this bit determines one of two panel resolutions when hr-tft is selected. this bit has no effect unless hr-tft is selected (reg[10h] bits 1:0 = 10). note this bit sets some internal non-configurable timing values for the selected panel. however, all panel configuration registers (reg[12h] ? reg[40h]) still require programming with the appropriate values for the selected panel. for panel ac timing, see section 10.4 ?display interface?.
solomon rev 1.3 10/2002 ssd1905 22 table 7-5 : active panel resolution selection active panel resolution select bit hr-tft resolution 0 160x160 1 320x240 bits 1-0 panel type bits[1:0] these bits select the panel type. table 7-6 : lcd panel type selection panel type bits [1:0] panel type 00 stn 01 tft 10 hr-tft 11 reserved mod rate register reg[11h] bit 7 6 5 4 3 2 1 0 0 0 mod rate bit 5 mod rate bit 4 mod rate bit 3 mod rate bit 2 mod rate bit 1 mod rate bit 0 type na na rw rw rw rw rw rw reset state 0 0 0 0 0 0 0 0 bits 5-0 mod rate bits [5:0] when these bits are all 0, the mod output signal (lden) toggles every lframe. for any non-zero value n, the mod output signal (lden) toggles every n lline. these bits are for passive lcd panels only. horizontal total register reg[12h] bit 7 6 5 4 3 2 1 0 0 horizontal total bit 6 horizontal total bit 5 horizontal total bit 4 horizontal total bit 3 horizontal total bit 2 horizontal total bit 1 horizontal total bit 0 type na rw rw rw rw rw rw rw reset state 0 0 0 0 0 0 0 0 bits 6-0 horizontal total bits [6:0] these bits specify the lcd panel horizontal total period, in 8 pixel resolution. the horizontal total is the sum of the horizontal display period and the horizontal non- display period. the maximum horizontal total is 1024 pixels. see figure 10-12 : panel timing parameters . horizontal total in number of pixels = (bits [6:0] + 1) x 8 note this register must be programmed such that the following condition is fulfilled. hdps + hdp < ht for panel ac timing and timing parameter definitions, see section 10.4 ?display interface?.
ssd1905 rev 1.3 10/2002 solomon 23 horizontal display period register reg[14h] bit 7 6 5 4 3 2 1 0 0 horizontal display period bit 6 horizontal display period bit 5 horizontal display period bit 4 horizontal display period bit 3 horizontal display period bit 2 horizontal display period bit 1 horizontal display period bit 0 type na rw rw rw rw rw rw rw reset state 0 0 0 0 0 0 0 0 bits 6-0 horizontal display period bits [6:0] these bits specify the lcd panel horizontal display period, in 8 pixel resolution. the horizontal display period should be less than the horizontal total to allow for a sufficient horizontal non-display period. horizontal display period in number of pixels = (bits [6:0] + 1) x 8 note maximum value of reg[14h] 0x3f when display rotate mode (90 or 270 ) is selected. for panel ac timing and timing parameter definitions, see section 10.4 ?display interface?. horizontal display period start position register 0 reg[16h] bit 7 6 5 4 3 2 1 0 horizontal display period start position bit 7 horizontal display period start position bit 6 horizontal display period start position bit 5 horizontal display period start position bit 4 horizontal display period start position bit 3 horizontal display period start position bit 2 horizontal display period start position bit 1 horizontal display period start position bit 0 type rw rw rw rw rw rw rw rw reset state 0 0 0 0 0 0 0 0 horizontal display period start position register 1 reg[17h] bit 7 6 5 4 3 2 1 0 0 0 0 0 0 0 horizontal display period start position bit 9 horizontal display period start position bit 8 type na na na na na na rw rw reset state 0 0 0 0 0 0 0 0 reg[17h] bits1-0, reg[16h] bits 7-0 horizontal display period start position bits [9:0] these bits specify the horizontal display period start position in 1 pixel resolution. note for panel ac timing and timing parameter definitions, see section 10.4 ?display interface?. vertical total register 0 reg[18h] bit 7 6 5 4 3 2 1 0 vertical total bit 7 vertical total bit 6 vertical total bit 5 vertical total bit 4 vertical total bit 3 vertical total bit 2 vertical total bit 1 vertical total bit 0 type rw rw rw rw rw rw rw rw reset state 0 0 0 0 0 0 0 0
solomon rev 1.3 10/2002 ssd1905 24 vertical total register 1 reg[19h] bit 7 6 5 4 3 2 1 0 0 0 0 0 0 0 vertical total bit 9 vertical total bit 8 type na na na na na na rw rw reset state 0 0 0 0 0 0 0 0 reg[19h] bits 1-0, reg[18h] bits 7-0 vertical total bits [9:0] these bits specify the lcd panel vertical total period, in 1 line resolution. the vertical total is the sum of the vertical display period and the vertical non-display period. the maximum vertical total is 1024 lines. see figure 10-12 : panel timing parameters . vertical total in number of lines = bits [9:0]+ 1 note this register must be programmed such that the following condition is fulfilled. for passive lcd interface : vdps + vdp + 1 < vt for other lcd interface : vdps + vdp < vt for panel ac timing and timing parameter definitions, see section 10.4 ?display interface?. vertical display period register 0 reg[1ch] bit 7 6 5 4 3 2 1 0 vertical display period bit 7 vertical display period bit 6 vertical display period bit 5 vertical display period bit 4 vertical display period bit 3 vertical display period bit 2 vertical display period bit 1 vertical display period bit 0 type rw rw rw rw rw rw rw rw reset state 0 0 0 0 0 0 0 0 vertical display period register 1 reg[1dh] bit 7 6 5 4 3 2 1 0 0 0 0 0 0 0 vertical display period bit 9 vertical display period bit 8 type na na na na na na rw rw reset state 0 0 0 0 0 0 0 0 reg[1dh] bits 1-0, reg[1ch] bits 7-0 vertical display period bits [9:0] these bits specify the lcd panel vertical display period, in 1 line resolution. the vertical display period should be less than the vertical total to allow for a sufficient vertical non-display period. vertical display period in number of lines = bits [9:0] + 1 note for panel ac timing and timing parameter definitions, see section 10.4 ?display interface?.
ssd1905 rev 1.3 10/2002 solomon 25 vertical display period start position register 0 reg[1eh] bit 7 6 5 4 3 2 1 0 vertical display period start position bit 7 vertical display period start position bit 6 vertical display period start position bit 5 vertical display period start position bit 4 vertical display period start position bit 3 vertical display period start position bit 2 vertical display period start position bit 1 vertical display period start position bit 0 type rw rw rw rw rw rw rw rw reset state 0 0 0 0 0 0 0 0 vertical display period start position register 1 reg[1fh] bit 7 6 5 4 3 2 1 0 0 0 0 0 0 0 vertical display start position period bit 9 vertical display start position period bit 8 type na na na na na na rw rw reset state 0 0 0 0 0 0 0 0 reg[1fh] bits 1-0, reg[1eh] bits 7-0 vertical display period start position bits [9:0] these bits specify the vertical display period start position in 1 line resolution. note for panel ac timing and timing parameter definitions, see section 10.4 ?display interface?. lline pulse width register reg[20h] bit 7 6 5 4 3 2 1 0 lline pulse polarity lline pulse width bit 6 lline pulse width bit 5 lline pulse width bit 4 lline pulse width bit 3 lline pulse width bit 2 lline pulse width bit 1 lline pulse width bit 0 type rw rw rw rw rw rw rw rw reset state 0 0 0 0 0 0 0 0 bit 7 lline pulse polarity this bit determines the polarity of the horizontal sync signal. the horizontal sync signal is typically named as lline or lp, depending on the panel type. when this bit = 0, the horizontal sync signal is active low. when this bit = 1, the horizontal sync signal is active high. bits 6-0 lline pulse width bits [6:0] these bits specify the width of the panel horizontal sync signal, in number of pclk. the horizontal sync signal is typically named as lline or lp, depending on the panel type. lline pulse width in pclk = bits [6:0] + 1 note for panel ac timing and timing parameter definitions, see section 10.4 ?display interface?.
solomon rev 1.3 10/2002 ssd1905 26 lline pulse start position register 0 reg[22h] bit 7 6 5 4 3 2 1 0 lline pulse start position bit 7 lline pulse start position bit 6 lline pulse start position bit 5 lline pulse start position bit 4 lline pulse start position bit 3 lline pulse start position bit 2 lline pulse start position bit 1 lline pulse start position bit 0 type rw rw rw rw rw rw rw rw reset state 0 0 0 0 0 0 0 0 lline pulse start position register 1 reg[23h] bit 7 6 5 4 3 2 1 0 0 0 0 0 0 0 lline pulse start position bit 9 lline pulse start position bit 8 type na na na na na na rw rw reset state 0 0 0 0 0 0 0 0 reg[23h] bits 1-0, reg[22h] bits 7-0 lline pulse start position bits [9:0] these bits specify the start position of the horizontal sync signal, in number of pclk. the maximum allowed value of lline pulse start position bits is 3feh. lline pulses start position in pclk = bits [9:0] + 1 note for panel ac timing and timing parameter definitions, see section10.4 ?display interface?. lframe pulse width register reg[24h] bit 7 6 5 4 3 2 1 0 lframe pulse polarity 0 0 0 0 lframe pulse width bit 2 lframe pulse width bit 1 lframe pulse width bit 0 type rw na na na na rw rw rw reset state 0 0 0 0 0 0 0 0 bit 7 lframe pulse polarity this bit selects the polarity of the vertical sync signal. the vertical sync signal is typically named as lframe or sps, depending on the panel typewhen this bit = 0, the vertical sync signal is active low. when this bit = 1, the vertical sync signal is active high. bits 2-0 lframe pulse width bits [2:0] these bits specify the width of the panel vertical sync signal, in 1 line resolution. the vertical sync signal is typically named as lframe or sps, depending on the panel type. the maximum allowed value of lframe pulse width bits is 6. lframe pulse width in number of pixels = (bits [2:0] + 1) x horizontal total + offset note for panel ac timing and timing parameter definitions, see section 10.4 ?display interface?.
ssd1905 rev 1.3 10/2002 solomon 27 lframe pulse start position register 0 reg[26h] bit 7 6 5 4 3 2 1 0 lframe pulse start position bit 7 lframe pulse start position bit 6 lframe pulse start position bit 5 lframe pulse start position bit 4 lframe pulse start position bit 3 lframe pulse start position bit 2 lframe pulse start position bit 1 lframe pulse start position bit 0 type rw rw rw rw rw rw rw rw reset state 0 0 0 0 0 0 0 0 lframe pulse start position register 1 reg[27h] bit 7 6 5 4 3 2 1 0 0 0 0 0 0 0 lframe pulse start position bit 9 lframe pulse start position bit 8 type na na na na na na rw rw reset state 0 0 0 0 0 0 0 0 reg[27h] bits 1-0 reg[26h] bits 7-0 lframe pulse start position bits [9:0] these bits specify the start position of the vertical sync signal, in 1 line resolution. lframe pulse start position in number of pixels = (bits [9:0]) x horizontal total + offset note for panel ac timing and timing parameter definitions, see section 10.4 ?display interface?. lframe pulse start offset register 0 reg[30h] bit 7 6 5 4 3 2 1 0 lframe start offset bit 7 lframe start offset bit 6 lframe start offset bit 5 lframe start offset bit 4 lframe start offset bit 3 lframe start offset bit 2 lframe start offset bit 1 lframe start offset bit 0 type rw rw rw rw rw rw rw rw reset state 0 0 0 0 0 0 0 0 lframe pulse start offset register 1 reg[31h] bit 7 6 5 4 3 2 1 0 0 0 0 0 0 0 lframe start offset bit 9 lframe start offset bit 8 type na na na na na na rw rw reset state 0 0 0 0 0 0 0 0 reg[31h] bits 1-0 reg[30h] bits 7-0 lframe pulse start offset [9:0] these bits specify the start offset of the vertical sync signal within a line, in 1 pixel resolution. note for panel ac timing and timing parameter definitions, see section 10.4 ?display interface?.
solomon rev 1.3 10/2002 ssd1905 28 lframe pulse stop offset register 0 reg[34h] bit 7 6 5 4 3 2 1 0 lframe stop offset bit 7 lframe stop offset bit 6 lframe stop offset bit 5 lframe stop offset bit 4 lframe stop offset bit 3 lframe stop offset bit 2 lframe stop offset bit 1 lframe stop offset bit 0 type rw rw rw rw rw rw rw rw reset state 0 0 0 0 0 0 0 0 lframe pulse stop offset register 1 reg[35h] bit 7 6 5 4 3 2 1 0 0 0 0 0 0 0 lframe stop offset bit 9 lframe stop offset bit 8 type na na na na na na rw rw reset state 0 0 0 0 0 0 0 0 reg[35h] bits 1-0 reg[34h] bits 7-0 lframe pulse stop offset [9:0] these bits specify the stop offset of the vertical sync signal within a line, in 1 pixel resolution. note for panel ac timing and timing parameter definitions, see section 10.4 ?display interface?. hr-tft special output register reg[38h] bit 7 6 5 4 3 2 1 0 0 0 gpio preset enable lshift polarity swap lshift mask gpio0 / gpio1 swap ps alternate cls double type na na rw rw rw rw rw rw reset state 0 0 0 0 0 0 0 0 bit 5 gpio preset enable when this bit = 1, gpio1 can be toggled once per line, gpio0 and gpio2 signals should be programmed with the appropriate values with reg[3ch], [3eh] and [40h]. when this bit = 0, gpio0, gpio1 and gpio2 signals are preset to defined values. bit 4 lshift polarity swap when this bit = 1, lshift signal is falling trigger. when this bit = 0, lshift signal is rising trigger. bit 3 lshift mask when this bit = 1, lshift signal is enabled in non display period. when this bit = 0, lshift signal is masked in non display period. bit 2 gpio0 / gpio1 swap when this bit = 1, gpio0 / gpio1 signals are swapped. when this bit = 0, gpio0 / gpio1 signals are not swapped. bit 1 ps alternate when this bit = 1, ps signal change alternatively. when this bit = 0, ps signal remain the same. bit 0 cls double when this bit = 1, number of cls pulse remain the same. when this bit = 0, number of cls pulse will be doubled. note
ssd1905 rev 1.3 10/2002 solomon 29 bit 5 is effective for 320x240 hr-tft panels only (reg[10h] bit 3 = 1, reg[10h] bits 1-0 = 10). if bit 4 is set to 1, lshift pin will be driven high at power saving mode. bits 4-2 are effective for hr-tft panels only (reg[10h] bits 1-0 = 10). bits 1-0 are effective for 160x160 hr-tft panels only (reg[10h] bit 3 = 0 and reg[10h] bits 1-0 = 10). for panel ac timing and timing parameter definitions, see section 10.4.8 ?160x160 sharp hr-tft panel timing (e.g. lq031b1ddxx)? and 10.4.9 ?320x240 sharp hr-tft panel timing (e.g. lq039q2ds01)?. gpio0 pulse start register reg[3ch] bit 7 6 5 4 3 2 1 0 gpio0 start bit 7 gpio0 start bit 6 gpio0 start bit 5 gpio0 start bit 4 gpio0 start bit 3 gpio0 start bit 2 gpio0 start bit 1 gpio0 start bit 0 type rw rw rw rw rw rw rw rw reset state 0 0 0 0 0 0 0 0 bits 7-0 gpio0 pulse start [7:0] these bits specify the start offset of the gpio0 signal within a line, in 1 pixel resolution. note this register is effective for 320x240 hr-tft panels and gpio preset enabled only (reg[10h] bit 3 = 1, reg[10h] bits 1-0 = 10 and reg[38h] bit 5 = 1). for panel ac timing and timing parameter definitions, see section 10.4.9 ?320x240 sharp hr-tft panel timing (e.g. lq039q2ds01)?. gpio0 pulse stop register reg[3eh] bit 7 6 5 4 3 2 1 0 gpio0 stop bit 7 gpio0 stop bit 6 gpio0 stop bit 5 gpio0 stop bit 4 gpio0 stop bit 3 gpio0 stop bit 2 gpio0 stop bit 1 gpio0 stop bit 0 type rw rw rw rw rw rw rw rw reset state 0 0 0 0 0 0 0 0 bits 7-0 gpio0 pulse stop [7:0] these bits specify the stop offset of the gpio0 signal within a line, in 1 pixel resolution. note this register is effective for 320x240 hr-tft panels and gpio preset enabled only (reg[10h] bit 3 = 1, reg[10h] bits 1-0 = 10 and reg[38h] bit 5 = 1). for panel ac timing and timing parameter definitions, see section 10.4.9 ?320x240 sharp hr-tft panel timing (e.g. lq039q2ds01)?.
solomon rev 1.3 10/2002 ssd1905 30 gpio2 pulse delay register reg[40h] bit 7 6 5 4 3 2 1 0 gpio2 delay bit 7 gpio2 delay bit 6 gpio2 delay bit 5 gpio2 delay bit 4 gpio2 delay bit 3 gpio2 delay bit 2 gpio2 delay bit 1 gpio2 delay bit 0 type rw rw rw rw rw rw rw rw reset state 0 0 0 0 0 0 0 0 bits 7-0 gpio2 pulse delay [7:0] these bits specify the pulse delay of the gpio2 signal within a line, in 1 pixel resolution. note this register is effective for 320x240 hr-tft panels and gpio preset enabled only (reg[10h] bit 3 = 1, reg[10h] bits 1-0 = 10 and reg[38h] bit 5 = 1). for panel ac timing and timing parameter definitions, see section 10.4.9 ?320x240 sharp hr-tft panel timing (e.g. lq039q2ds01)?. stn color depth control register reg[45h] bit 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 stn color depth control type na na na na na na na rw reset state 0 0 0 0 0 0 0 0 bit 0 stn color depth control this bit controls the maximum number of color available for stn panels. when this bit = 0, it allows maximum 32k color depth. when this bit = 1, it allows maximum 256k color depth. please refer to table 7-8 : lcd bit-per-pixel selection for the color depth relationship. note reg[45h] is effective for stn panel only (reg[10h] bits 1:0 = 00).
ssd1905 rev 1.3 10/2002 solomon 31 dynamic dithering control register reg[50h] bit 7 6 5 4 3 2 1 0 dynamic dithering enable 0 0 0 0 0 0 1 type rw na na na na na na ro reset state 0 0 0 0 0 0 0 1 bit 7 dynamic dithering enable this bit will enable the dynamic dithering, the dithering mask will change after each 16 frames. when this bit = 0, dynamic dithering is disabled. when this bit = 1, dynamic dithering is enabled. note reg[45h] is effective for both stn panel and dithering enabled (reg[10h] bits 1:0 = 00 and reg[70h] bit 6 = 0). 7.2.5 display mode registers display mode register reg[70h] bit 7 6 5 4 3 2 1 0 display blank dithering disable hardware color invert enable software color invert 0 bit-per-pixel select bit 2 bit-per-pixel select bit 1 bit-per-pixel select bit 0 type rw rw rw rw na rw rw rw reset state 0 0 0 0 0 0 0 0 bit 7 display blank when this bit = 0, the lcd display output is enabled. when this bit = 1, the lcd display output is blank and all lcd data outputs are forced to zero (i.e., the screen is blanked). bit 6 dithering disable ssd1905 use a combination of frc and 4 pixel square formation dithering to achieve more colors per pixel. when this bit = 0, dithering is enabled on the passive lcd panel. it allows maximum 64 intensity levels for each color component (rgb). when this bit = 1, dithering is disabled on the passive lcd panel. it allows maximum 16 intensity levels for each color component (rgb). note this bit does not refer to the number of simultaneously displayed colors but rather the maximum available colors (refer table 7-8 : lcd bit-per-pixel selection for the maximum number of displayed colors).
solomon rev 1.3 10/2002 ssd1905 32 bit 5 hardware color invert enable this bit allows the color invert feature to be controlled using the general purpose io pin gpio0. this bit has no effect if reg[70h] bit 7 = 1. this option is not available if configured for a hr-tft as gpio0 is used as an lcd control signal. when this bit = 0, gpio0 has no effect on the display color. when this bit = 1, display color may be inverted via gpio0. note display color is inverted after the look-up table. the ssd1905 requires some configurations before the hardware color invert feature enabled. ? cf3 must be set to 1 during reset# is active ? gpio pin input enable (reg[a9h] bit 7) must be set to 1 ? gpio0 pin io configuration (reg[a8h] bit 0) must be set to 0 if hardware color invert is not available (i.e. hr-tft panel is used), the color invert function can be controlled by software using reg[70h] bit 4. table 7-7 : color invert mode options summarizes the color invert options available. bit 4 software color invert when this bit = 0, display color is normal. when this bit = 1, display color is inverted. see table 7-7 : color invert mode options. this bit has no effect if reg[70h] bit 7 = 1 or reg[70h] bit 5 = 1. note display color is inverted after the look-up table. table 7-7 : color invert mode options hardware color invert enable software color invert gpio0 display color 0 0 x normal 0 1 x invert 1 x 0 normal 1 x 1 invert x = don?t care bits 2-0 bit-per-pixel select bits [2:0] these bits select the color depth (bit-per-pixel) for the displayed data for both the main window and the floating window (if active). note 1, 2, 4 and 8 bpp modes use the 18-bit lut, allowing maximum 256k colors. 16 bpp mode bypasses the lut, allowing 64k colors.
ssd1905 rev 1.3 10/2002 solomon 33 table 7-8 : lcd bit-per-pixel selection maximum number of colors/shades passive panel (dithering on) bit-per-pixel select bits [2:0] color depth (bpp) reg[45h] bit 0 = 0 reg[45h] bit 0 = 1 tft panel max. no. of simultaneously displayed colors/shades 000 1 bpp 32k/32 256k/64 256k/64 2/2 001 2 bpp 32k/32 256k/64 256k/64 4/4 010 4 bpp 32k/32 256k/64 256k/64 16/16 011 8 bpp 32k/32 256k/64 256k/64 256/64 100 16 bpp 32k/32 64k/64 64k/64 64k/64 101, 110, 111 reserved n/a n/a n/a n/a special effects register reg[71h] bit 7 6 5 4 3 2 1 0 display data word swap display data byte swap 0 floating window enable 0 0 display rotate mode select bit 1 display rotate mode select bit 0 type rw rw na rw na na rw rw reset state 0 0 0 0 0 0 0 0 bit 7 display data word swap the display pipe fetches 32-bit of data from the display buffer. this bit enables the lower 16-bit word and the upper 16-bit word to be swapped before sending them to the lcd display. if the display data byte swap bit is also enabled, then the byte order of the fetched 32-bit data is reversed. bit 6 display data byte swap the display pipe fetches 32-bit of data from the display buffer. this bit enables swapping of byte 0 and byte 1, byte 2 and byte 3, before sending them to the lcd. if the display data word swap bit is also set, then the byte order of the fetched 32-bit data is reversed. note for further information on byte swapping for big endian mode, see section 16 ?big-endian bus interface?. data serialization 32-bit display data from display buffer word swap byte swap to lut byte 0 byte 1 byte 2 byte 3 figure 7-1 : display data byte/word swap
solomon rev 1.3 10/2002 ssd1905 34 bit 4 floating window enable this bit enables the floating window within the main window used for the floating window feature. the location of the floating window within the main window is determined by the floating window position x registers (reg[84h], reg[85h], reg[8ch], reg[8dh]) and floating window position y registers (reg[88h], reg[89h], reg[90h], reg[91h]). the floating window has its own display start address register (reg[7ch, reg[7dh], reg[7eh]) and memory address offset register (reg[80h], reg[81h]). the floating window shares the same color depth and display orientation as the main window. when this bit = 1, floating window is enabled. when this bit = 0, floating window is disabled. bits 1-0 display rotate mode select bits [1:0] these bits select different display orientations: table 7-9 : display rotate mode select options display rotate mode select bits [1:0] display orientation 00 0 (normal) 01 90 10 180 11 270 main window display start address register 0 reg[74h] bit 7 6 5 4 3 2 1 0 main window display start address bit 7 main window display start address bit 6 main window display start address bit 5 main window display start address bit 4 main window display start address bit 3 main window display start address bit 2 main window display start address bit 1 main window display start address bit 0 type rw rw rw rw rw rw rw rw reset state 0 0 0 0 0 0 0 0 main window display start address register 1 reg[75h] bit 7 6 5 4 3 2 1 0 main window display start address bit 15 main window display start address bit 14 main window display start address bit 13 main window display start address bit 12 main window display start address bit 11 main window display start address bit 10 main window display start address bit 9 main window display start address bit 8 type rw rw rw rw rw rw rw rw reset state 0 0 0 0 0 0 0 0
ssd1905 rev 1.3 10/2002 solomon 35 main window display start address register 2 reg[76h] bit 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 main window display start address bit 16 type na na na na na na na rw reset state 0 0 0 0 0 0 0 0 reg[76h] bit 0, reg[75h] bits 7-0, reg[74h] bits 7-0 main window display start address bits [16:0] these bits form the 17-bit address for the starting double-word of the lcd image in the display buffer for the main window. note that this is a double-word (32-bit) address. an entry of 00000h into these registers represents the first double-word of display memory, an entry of 00001h represents the second double-word of the display memory, and so on. calculate the display start address as follows : main window display start address bits 16:0 = image address 4 (valid only for display rotate mode 0 ) note for information on setting this register for other display rotate mode, see section 18 ?display rotate mode?. main window line address offset register 0 reg[78h] bit 7 6 5 4 3 2 1 0 main window line address offset bit 7 main window line address offset bit 6 main window line address offset bit 5 main window line address offset bit 4 main window line address offset bit 3 main window line address offset bit 2 main window line address offset bit 1 main window line address offset bit 0 type rw rw rw rw rw rw rw rw reset state 0 0 0 0 0 0 0 0 main window line address offset register 1 reg[79h] bit 7 6 5 4 3 2 1 0 0 0 0 0 0 0 main window line address offset bit 9 main window line address offset bit 8 type na na na na na na rw rw reset state 0 0 0 0 0 0 0 0
solomon rev 1.3 10/2002 ssd1905 36 reg[79h] bits 1-0, reg[78h] bits 7-0 main window line address offset bits [9:0] this register specifies the offset, in double words, from the beginning of one display line to the beginning of the next display line in the main window. note that this is a 32-bit address increment. calculate the line address offset as follows : main window line address offset bits 9-0 = display width in pixels (32 bpp) note a virtual display can be created by programming this register with a value greater than the formula requires. when a virtual display is created the image width is larger than the display width and the displayed image becomes a window into the larger virtual image. 7.2.6 floating window registers floating window display start address register 0 reg[7ch] bit 7 6 5 4 3 2 1 0 floating window display start address bit 7 floating window display start address bit 6 floating window display start address bit 5 floating window display start address bit 4 floating window display start address bit 3 floating window display start address bit 2 floating window display start address bit 1 floating window display start address bit 0 type rw rw rw rw rw rw rw rw reset state 0 0 0 0 0 0 0 0 floating window display start address register 1 reg[7dh] bit 7 6 5 4 3 2 1 0 floating window display start address bit 15 floating window display start address bit 14 floating window display start address bit 13 floating window display start address bit 12 floating window display start address bit 11 floating window display start address bit 10 floating window display start address bit 9 floating window display start address bit 8 type rw rw rw rw rw rw rw rw reset state 0 0 0 0 0 0 0 0 floating window display start address register 2 reg[7eh] bit 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 floating window display start address bit 16 type na na na na na na na rw reset state 0 0 0 0 0 0 0 0
ssd1905 rev 1.3 10/2002 solomon 37 reg[7eh] bit 0, reg[7dh] bits 7-0 reg[7ch] bits 7-0 floating window display start address bits [16:0] these bits form the 17-bit address for the starting double-word of the floating window. note that this is a double-word (32-bit) address. an entry of 00000h into these registers represents the first double-word of display memory, an entry of 00001h represents the second double-word of the display memory, and so on. note these bits will not effective until the floating window enable bit is set to 1 (reg[71h] bit 4=1). floating window line address offset register 0 reg[80h] bit 7 6 5 4 3 2 1 0 floating window line address offset bit 7 floating window line address offset bit 6 floating window line address offset bit 5 floating window line address offset bit 4 floating window line address offset bit 3 floating window line address offset bit 2 floating window line address offset bit 1 floating window line address offset bit 0 type rw rw rw rw rw rw rw rw reset state 0 0 0 0 0 0 0 0 floating window line address offset register 1 reg[81h] bit 7 6 5 4 3 2 1 0 0 0 0 0 0 0 floating window line address offset bit 9 floating window line address offset bit 8 type na na na na na na rw rw reset state 0 0 0 0 0 0 0 0 reg[81h] bits 1-0, reg[80h] bits 7-0 floating window line address offset bits [9:0] these bits are the lcd display?s 10-bit address offset from the starting double-word of line ?n? to the starting double-word of line ?n + 1? for the floating window. note that this is a 32-bit address increment. note these bits will not effective until the floating window enable bit is set to 1 (reg[71h] bit 4=1). floating window start position x register 0 reg[84h] bit 7 6 5 4 3 2 1 0 floating window start x position bit 7 floating window start x position bit 6 floating window start x position bit 5 floating window start x position bit 4 floating window start x position bit 3 floating window start x position bit 2 floating window start x position bit 1 floating window start x position bit 0 type rw rw rw rw rw rw rw rw reset state 0 0 0 0 0 0 0 0
solomon rev 1.3 10/2002 ssd1905 38 floating window start position x register 1 reg[85h] bit 7 6 5 4 3 2 1 0 0 0 0 0 0 0 floating window start x position bit 9 floating window start x position bit 8 type na na na na na na rw rw reset state 0 0 0 0 0 0 0 0 reg[85h] bits 1-0, reg[84h] bits 7-0 floating window start position x bits [9:0] these bits determine the start position x of the floating window in relation to the origin of the panel. due to the ssd1905 display rotate feature, the start position x may not be a horizontal position value (only true in 0 and 180 rotation). for further information on defining the value of the start position x register, see section 19 ?floating window mode?. the value of register is also increased differently based on the display orientation. for 0 and 180 display rotate mode, the start position x is incremented by x pixels where x is relative to the current color depth. for 90 and 270 display rotate mode, the start position x is incremented by 1 line. depending on the color depth, some of the higher bits in this register are unused because the maximum horizontal display width is 1024 pixels. note these bits will not effective until the floating window enable bit is set to 1 (reg[71h] bit 4=1). table 7-10 : 32-bit address x increments for various color depths color depth (bpp) pixel increment (x) 1 32 2 16 4 8 8 4 16 2 floating window start position y register 0 reg[88h] bit 7 6 5 4 3 2 1 0 floating window start y position bit 7 floating window start y position bit 6 floating window start y position bit 5 floating window start y position bit 4 floating window start y position bit 3 floating window start y position bit 2 floating window start y position bit 1 floating window start y position bit 0 type rw rw rw rw rw rw rw rw reset state 0 0 0 0 0 0 0 0
ssd1905 rev 1.3 10/2002 solomon 39 floating window start position y register 1 reg[89h] bit 7 6 5 4 3 2 1 0 0 0 0 0 0 0 floating window start y position bit 9 floating window start y position bit 8 type na na na na na na rw rw reset state 0 0 0 0 0 0 0 0 reg[89h] bits 1-0, reg[88h] bits 7-0 floating window start position y bits [9:0] these bits determine the start position y of the floating window in relation to the origin of the panel. due to the ssd1905 display rotate feature, the start position y may not be a vertical position value (only true in 0 and 180 floating window). for further information on defining the value of the start position y register, see section 19 ?floating window mode?. the register is also incremented according to the display orientation. for 0 and 180 display rotate mode, the start position y is incremented by 1 line. for 90 and 270 display rotate mode, the start position y is incremented by y pixels where y is relative to the current color depth. depending on the color depth, some of the higher bits in this register are unused because the maximum vertical display height is 1024 pixels. note these bits will not effective until the floating window enable bit is set to 1 (reg[71h] bit 4=1). table 7-11 : 32-bit address y increments for various color depths color depth (bpp) pixel increment (y) 1 32 2 16 4 8 8 4 16 2 floating window end position x register 0 reg[8ch] bit 7 6 5 4 3 2 1 0 floating window end x position bit 7 floating window end x position bit 6 floating window end x position bit 5 floating window end x position bit 4 floating window end x position bit 3 floating window end x position bit 2 floating window end x position bit 1 floating window end x position bit 0 type rw rw rw rw rw rw rw rw reset state 0 0 0 0 0 0 0 0
solomon rev 1.3 10/2002 ssd1905 40 floating window end position x register 1 reg[8dh] bit 7 6 5 4 3 2 1 0 0 0 0 0 0 0 floating window end x position bit 9 floating window end x position bit 8 type na na na na na na rw rw reset state 0 0 0 0 0 0 0 0 reg[8dh] bits 1-0, reg[8ch] bits 7-0 floating window end position x bits [9:0] these bits determine the end position x of the floating window in relation to the origin of the panel. due to the ssd1905 display rotate feature, the end position x may not be a horizontal position value (only true in 0 and 180 rotation). for further information on defining the value of the end position x register, see 19 ?floating window mode?. the value of register is also increased according to the display orientation. for 0 and 180 display rotate mode, the end position x is incremented by x pixels where x is relative to the current color depth. for 90 and 270 display rotate mode, the end position x is incremented by 1 line. depending on the color depth, some of the higher bits in this register are unused because the maximum horizontal display width is 1024 pixels. note these bits will not effective until the floating window enable bit is set to 1 (reg[71h] bit 4=1). table 7-12 : 32-bit address x increments for various color depths color depth (bpp) pixel increment (x) 1 32 2 16 4 8 8 4 16 2 floating window end position y register 0 reg[90h] bit 7 6 5 4 3 2 1 0 floating window end y position bit 7 floating window end y position bit 6 floating window end y position bit 5 floating window end y position bit 4 floating window end y position bit 3 floating window end y position bit 2 floating window end y position bit 1 floating window end y position bit 0 type rw rw rw rw rw rw rw rw reset state 0 0 0 0 0 0 0 0
ssd1905 rev 1.3 10/2002 solomon 41 floating window end position y register 1 reg[91h] bit 7 6 5 4 3 2 1 0 0 0 0 0 0 0 floating window end y position bit 9 floating window end y position bit 8 type na na na na na na rw rw reset state 0 0 0 0 0 0 0 0 reg[91h] bits 1-0, reg[90h] bits 7-0 floating window end position y bits [9:0] the panel. due to the ssd1905 display rotate feature, the end position y may not be a vertical position value (only true in 0 and 180 display rotate mode). for further information on defining the value of the end position y register, see section 19 ?floating window mode?. the value of register is also increased according to the display orientation. for 0 and 180 display rotate mode, the end position y is incremented by 1 line. for 90 and 270 display rotate mode, the end position y is incremented by y pixels where y is relative to the current color depth. depending on the color depth, some of the higher bits in this register are unused because the maximum vertical display height is 1024 pixels. note these bits will not effective until the floating window enable bit is set to 1 (reg[71h] bit 4=1). table 7-13 : 32-bit address y increments for various color depths color depth (bpp) pixel increment (y) 1 32 2 16 4 8 8 4 16 2 7.2.7 miscellaneous registers power saving configuration register reg[a0h] bit 7 6 5 4 3 2 1 0 vertical non- display period status 0 0 0 memory controller power saving status 0 0 power saving mode enable type ro na na na ro na na rw reset state 1 0 0 0 0 0 0 1
solomon rev 1.3 10/2002 ssd1905 42 bit 7 vertical non-display period status when this bit = 0, the lcd panel is in vertical display period. when this bit = 1, the lcd panel is in vertical non-display period. bit 3 memory controller power saving status this bit indicates the power saving status of the memory controller. when this bit = 0, the memory controller is powered up. when this bit = 1, the memory controller is powered down. bit 0 power saving mode enable when this bit = 1, power saving mode is enabled. when this bit = 0, power saving mode is disabled. software reset register reg[a2h] bit 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 software reset type na na na na na na na wo reset state 0 0 0 0 0 0 0 0 bit 0 software reset when a one is written to this bit, the ssd1905 registers are reset . this bit has no effect on the contents of the display buffer. scratch pad register 0 reg[a4h] bit 7 6 5 4 3 2 1 0 scratch pad bit 7 scratch pad bit 6 scratch pad bit 5 scratch pad bit 4 scratch pad bit 3 scratch pad bit 2 scratch pad bit 1 scratch pad bit 0 type rw rw rw rw rw rw rw rw reset state 0 0 0 0 0 0 0 0 scratch pad register 1 reg[a5h] bit 7 6 5 4 3 2 1 0 scratch pad bit 15 scratch pad bit 14 scratch pad bit 13 scratch pad bit 12 scratch pad bit 11 scratch pad bit 10 scratch pad bit 9 scratch pad bit 8 type rw rw rw rw rw rw rw rw reset state 0 0 0 0 0 0 0 0 reg[a5h] bits 7-0, reg[a4h] bits 7-0 scratch pad bits [15:0] this register contains general purpose read/write bits. these bits have no effect on hardware configuration.
ssd1905 rev 1.3 10/2002 solomon 43 7.2.8 general io pins registers general purpose i/o pins configuration register 0 reg[a8h] bit 7 6 5 4 3 2 1 0 0 gpio6 i/o configuration gpio5 i/o configuration gpio4 i/o configuration gpio3 i/o configuration gpio2 i/o configuration gpio1 i/o configuration gpio0 i/o configuration type na rw rw rw rw rw rw rw reset state 0 0 0 0 0 0 0 0 bit 6 gpio6 i/o configuration when this bit = 0, gpio6 is configured as an input pin. when this bit = 1, gpio6 is configured as an output pin. bit 5 gpio5 i/o configuration when this bit = 0, gpio5 is configured as an input pin. when this bit = 1, gpio5 is configured as an output pin. bit 4 gpio4 i/o configuration when this bit = 0, gpio4 is configured as an input pin. when this bit = 1, gpio4 is configured as an output pin. bit 3 gpio3 i/o configuration when this bit = 0, gpio3 is configured as an input pin. when this bit = 1, gpio3 is configured as an output pin. bit 2 gpio2 i/o configuration when this bit = 0, gpio2 is configured as an input pin. when this bit = 1, gpio2 is configured as an output pin. bit 1 gpio1 i/o configuration when this bit = 0, gpio1 is configured as an input pin. when this bit = 1, gpio1 is configured as an output pin. bit 0 gpio0 i/o configuration when this bit = 0, gpio0 is configured as an input pin. when this bit = 1, gpio0 is configured as an output pin. note if cf3 = 0 during reset# is active, then all gpio pins are configured as outputs only and this register has no effect. this case allows the gpio pins to be used by the hr-tft panel interfaces. for a summary of gpio usage for hr-tft, see table 5-8 : lcd interface pin mapping. the input functions of the gpio pins are not enabled until reg[a9h] bit 7 is set to 1.
solomon rev 1.3 10/2002 ssd1905 44 general purpose io pins configuration register 1 reg[a9h] bit 7 6 5 4 3 2 1 0 gpio pin input enable 0 0 0 0 0 0 0 type rw na na na na na na na reset state 0 0 0 0 0 0 0 0 bit 7 gpio pin input enable this bit is used to enable the input function of the gpio pins. it must be changed to a 1 after power-on reset to enable the input function of the gpio pins. general purpose io pins status/control register 0 reg[ach] bit 7 6 5 4 3 2 1 0 0 gpio6 pin io status gpio5 pin io status gpio4 pin io status gpio3 pin io status gpio2 pin io status gpio1 pin io status gpio0 pin io status type na rw rw rw rw rw rw rw reset state 0 0 0 0 0 0 0 0 note for information on gpio pin mapping when hr-tft panels are selected, see table 5-2 : lcd interface pin descriptions. bit 6 gpio6 pin io status when gpio6 is configured as an output, writing a 1 to this bit drives gpio6 high and writing a 0 to this bit drives gpio6 low. when gpio6 is configured as an input, a read from this bit returns the status of gpio6. bit 5 gpio5 pin io status when gpio5 is configured as an output, writing a 1 to this bit drives gpio5 high and writing a 0 to this bit drives gpio5 low. when gpio5 is configured as an input, a read from this bit returns the status of gpio5. bit 4 gpio4 pin io status when gpio4 is configured as an output, writing a 1 to this bit drives gpio4 high and writing a 0 to this bit drives gpio4 low. when gpio4 is configured as an input, a read from this bit returns the status of gpio4. bit 3 gpio3 pin io status when a hr-tft panel is not selected (reg[10h] bits 1:0=00/01/11) and gpio3 is configured as an output, writing a 1 to this bit drives gpio3 high and writing a 0 to this bit drives gpio3 low. when a hr-tft panel is not selected (reg[10h] bits 1:0=00/01/11) and gpio3 is configured as an input, a read from this bit returns the status of gpio3. when a hr-tft panel is enabled (reg[10h] bits 1:0 = 10), the hr-tft signal spl signal is enabled whatever the value of this bit.
ssd1905 rev 1.3 10/2002 solomon 45 bit 2 gpio2 pin io status when a hr-tft panel is not selected (reg[10h] bits 1:0=00/01/11) and gpio2 is configured as an output, writing a 1 to this bit drives gpio2 high and writing a 0 to this bit drives gpio2 low. when a hr-tft panel is not selected (reg[10h] bits 1:0=00/01/11) and gpio2 is configured as an input, a read from this bit returns the status of gpio2. when a hr-tft panel is enabled (reg[10h] bits 1:0 = 10), the hr-tft signal rev signal is enabled whatever the value of this bit. bit 1 gpio1 pin io status when a hr-tft panel is not selected (reg[10h] bits 1:0=00/01/11) and gpio1 is configured as an output, writing a 1 to this bit drives gpio1 high and writing a 0 to this bit drives gpio1 low. when a hr-tft panel is not selected (reg[10h] bits 1:0=00/01/11) and gpio1 is configured as an input, a read from this bit returns the status of gpio1. when a hr-tft panel is enabled (reg[10h] bits 1:0 = 10), the hr-tft signal cls signal is enabled whatever the value of this bit. bit 0 gpio0 pin io status when a hr-tft panel is not selected (reg[10h] bits 1:0=00/01/11) and gpio0 is configured as an output, writing a 1 to this bit drives gpio0 high and writing a 0 to this bit drives gpio0 low. when a hr-tft is not selected (reg[10h] bits 1:0=00/01/11) and gpio0 is configured as an input, a read from this bit returns the status of gpio0. when a hr-tft panel is enabled (reg[10h] bits 1:0 = 10), the hr-tft signal ps signal is enabled whatever the value of this bit. general purpose io pins status/control register 1 reg[adh] bit 7 6 5 4 3 2 1 0 gpo control 0 0 0 0 0 0 0 type rw na na na na na na na reset state 0 0 0 0 0 0 0 0 bit 7 gpo control this bit controls the general purpose output pin. writing a 0 to this bit drives gpo to low. writing a 1 to this bit drives gpo to high. note many implementations use the gpo pin to control the lcd bias power (see section 10.3,?lcd power sequencing?).
solomon rev 1.3 10/2002 ssd1905 46 7.2.9 pulse width modulation (pwm) clock and contrast voltage (cv) pulse configuration registers pwm clock divider clock source/ 2 m pwmclk m = pwm clock divide select value x = cv pulse divide select value cv pulse divider clock source/ 2 x pwm clock force hi g h cv pulse enable divided clock divided clock pwm clock enable pwm duty cycle modulation duty = n / 256 cv pulse burst generation y-pulse burst y = burst length value cv pulse force hi g h lpwmout lcvout frequency = clock source / (2 m x 256) frequency = clock source / (2 x x 2) n = pwm clock duty cycle figure 7-2 : pwm clock/cv pulse block diagram note for further information on pwmclk, see section 11.1.4 ?pwmclk?. pwm clock / cv pulse control register reg[b0h] bit 7 6 5 4 3 2 1 0 pwm clock force high 0 0 pwm clock enable cv pulse force high cv pulse burst status cv pulse burst start cv pulse enable type rw na na rw rw ro rw rw reset state 0 0 0 0 0 0 0 0 bit 7 and bit 4 pwm clock force high (bit 7) and pwm clock enable (bit 4) these bits control the lpwmout and pwm clock circuitry as table 7-14 : pwm clock control. when lpwmout is forced low or forced high it can be used as a general purpose output. note the pwm clock circuitry is disabled when power saving mode is enabled. table 7-14 : pwm clock control bit 7 bit 4 result 0 1 pwm clock circuitry enabled (controlled by reg[b1h] and reg[b3h]) 0 0 lpwmout forced low 1 x lpwmout forced high x = don?t care
ssd1905 rev 1.3 10/2002 solomon 47 bit 3 and bit 0 cv pulse force high (bit 3) and cv pulse enable (bit 0) these bits control the lcvout pin and cv pulse circuitry as table 7-15 : cv pulse control. when lcvout is forced low or forced high it can be used as a general purpose output. note bit 3 must be set to 0 and bit 0 must be set to 1 before initiating a new burst using the cv pulse burst start bit. the cv pulse circuitry is disabled when power saving mode is enabled. table 7-15 : cv pulse control bit 3 bit 0 result 0 1 cv pulse circuitry enabled (controlled by reg[b1h] and reg[b2h]) 0 0 lcvout forced low 1 x lcvout forced high x = don?t care bit 2 cv pulse burst status a ?1? indicates a cv pulse burst is occurring. a ?0? indicates no cv pulse burst is occurring. software should wait for this bit to clear before starting another burst. bit 1 cv pulse burst start a ?1? in this bit initiates a single lcvout pulse burst. the number of clock pulses generated is programmable from 1 to 256. the frequency of the pulses is the divided cv pulse source divided by 2, with 50/50 duty cycle. this bit should be cleared to 0 by software before initiating a new burst. note this bit has effect only if the cv pulse enable bit is 1. pwm clock / cv pulse configuration register reg[b1h] bit 7 6 5 4 3 2 1 0 pwm clock divide select bit 3 pwm clock divide select bit 2 pwm clock divide select bit 1 pwm clock divide select bit 0 cv pulse divide select bit 2 cv pulse divide select bit 1 cv pulse divide select bit 0 pwmclk source select type rw rw rw rw rw rw rw rw reset state 0 0 0 0 0 0 0 0 bits 7-4 pwm clock divide select bits [3:0] the value of these bits represents the power of 2 by which the selected pwm clock source is divided. note this divided clock is further divided by 256 before it is output at lpwmout. table 7-16 : pwm clock divide select options pwm clock divide select bits [3:0] pwm clock divide amount 0h 1 1h 2 2h 4 3h 8 ... ... ch 4096 dh-fh 1
solomon rev 1.3 10/2002 ssd1905 48 bits 3-1 cv pulse divide select bits [2:0] the value of these bits represents the power of 2 by which the selected cv pulse source is divided. note this divided clock is further divided by 2 before it is output at the lcvout. table 7-17 : cv pulse divide select options cv pulse divide select bits [2:0] cv pulse divide amount 0h 1 1h 2 2h 4 3h 8 ... ... 7h 128 bit 0 pwmclk source select when this bit = 0, the clock source for pwmclk is clki. when this bit = 1, the clock source for pwmclk is auxclk. note for further information on the pwmclk source select, see section 11 ?clocks?. cv pulse burst length register reg[b2h] bit 7 6 5 4 3 2 1 0 cv pulse burst length bit 7 cv pulse burst length bit 6 cv pulse burst length bit 5 cv pulse burst length bit 4 cv pulse burst length bit 3 cv pulse burst length bit 2 cv pulse burst length bit 1 cv pulse burst length bit 0 type rw rw rw rw rw rw rw rw reset state 0 0 0 0 0 0 0 0 bits 7-0 cv pulse burst length bits [7:0] the value of this register determines the number of pulses generated in a single cv pulse burst: number of pulses in a burst = bits [7:0] + 1 pwm duty cycle register reg[b3h] bit 7 6 5 4 3 2 1 0 pwm duty cycle bit 7 pwm duty cycle bit 6 pwm duty cycle bit 5 pwm duty cycle bit 4 pwm duty cycle bit 3 pwm duty cycle bit 2 pwm duty cycle bit 1 pwm duty cycle bit 0 type rw rw rw rw rw rw rw rw reset state 0 0 0 0 0 0 0 0 bits 7-0 pwm duty cycle bits [7:0] this register determines the duty cycle of the pwm output.
ssd1905 rev 1.3 10/2002 solomon 49 table 7-18 : pwm duty cycle select options pwm duty cycle [7:0] pwm duty cycle 00h always low 01h high for 1 out of 256 clock periods 02h high for 2 out of 256 clock periods ? ? ffh high for 255 out of 256 clock periods. 7.2.10 cursor mode registers cursor feature register reg[c0h] bit 7 6 5 4 3 2 1 0 cursor1 enable cursor2 enable 0 0 0 0 0 0 type rw rw na na na na na na reset state 0 0 0 0 0 0 0 0 bit 7 cursor1 enable when this bit = 0 cursor1 is disabled. when this bit = 1 cursor1 is enabled. bit 6 cursor2 enable when this bit = 0, cursor2 is disabled. when this bit = 1, cursor2 is enabled. note this register is effective for 4/8/16 bpp (reg[70h] bits 2:0 = 010/011/100) for hardware cursors operation, see section 20 ?hardware cursor mode?. cursor1 blink total register 0 reg[c4h] bit 7 6 5 4 3 2 1 0 cursor1 blink total bit 7 cursor1 blink total bit 6 cursor1 blink total bit 5 cursor1 blink total bit 4 cursor1 blink total bit 3 cursor1 blink total bit 2 cursor1 blink total bit 1 cursor1 blink total bit 0 type rw rw rw rw rw rw rw rw reset state 0 0 0 0 0 0 0 0 cursor1 blink total register 1 reg[c5h] bit 7 6 5 4 3 2 1 0 0 0 0 0 0 0 cursor1 blink total bit 9 cursor1 blink total bit 8 type na na na na na na rw rw reset state 0 0 0 0 0 0 0 0 reg[c5h] bits 1-0, reg[c4h] bits 7-0 cursor1 blink total bits [9:0] this is the total blinking period per frame for cursor1. this register must be set to a non-zero value in order to make the cursor visible. note these bits will not effective until the cursor1 enable bit is set to 1 (reg[c0h] bit 7=1).
solomon rev 1.3 10/2002 ssd1905 50 cursor1 blink on register 0 reg[c8h] bit 7 6 5 4 3 2 1 0 cursor1 blink on bit 7 cursor1 blink on bit 6 cursor1 blink on bit 5 cursor1 blink on bit 4 cursor1 blink on bit 3 cursor1 blink on bit 2 cursor1 blink on bit 1 cursor1 blink on bit 0 type rw rw rw rw rw rw rw rw reset state 0 0 0 0 0 0 0 0 cursor1 blink on register 1 reg[c9h] bit 7 6 5 4 3 2 1 0 0 0 0 0 0 0 cursor1 blink on bit 9 cursor1 blink on bit 8 type na na na na na na rw rw reset state 0 0 0 0 0 0 0 0 reg[c9h] bits 1-0, reg[c8h] bits 7-0 cursor1 blink on bits [9:0] this is the blink on frame period for cursor1. this register must be set to a non-zero value in order to make the cursor1 visible. also, cursor1 will start to blink if the following conditions are fulfilled : cursor1 blink total bits [9:0] > cursor1 blink on bits [9:0] > 0 note: to enable cursor1 without blinking, user must program cursor1 blink on register with a non-zero value, and this value must be greater than or equal to cursor1 blink total register. these bits will not effective until the cursor1 enable bit is set to 1 (reg[c0h] bit 7=1). cursor1 memory start register 0 reg[cch] bit 7 6 5 4 3 2 1 0 cursor1 memory start bit 7 cursor1 memory start bit 6 cursor1 memory start bit 5 cursor1 memory start bit 4 cursor1 memory start bit 3 cursor1 memory start bit 2 cursor1 memory start bit 1 cursor1 memory start bit 0 type rw rw rw rw rw rw rw rw reset state 0 0 0 0 0 0 0 0 cursor1 memory start register 1 reg[cdh] bit 7 6 5 4 3 2 1 0 cursor1 memory start bit 15 cursor1 memory start bit 14 cursor1 memory start bit 13 cursor1 memory start bit 12 cursor1 memory start bit 11 cursor1 memory start bit 10 cursor1 memory start bit 9 cursor1 memory start bit 8 type rw rw rw rw rw rw rw rw reset state 0 0 0 0 0 0 0 0 cursor1 memory start register 2 reg[ceh] bit 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 cursor1 memory start bit 16 type na na na na na na na rw reset state 0 0 0 0 0 0 0 0
ssd1905 rev 1.3 10/2002 solomon 51 reg[ceh] bit 0, reg[cdh] bits 7-0 reg[cch] bits 7-0 cursor1 memory start bits [16:0] this is the start location of memory buffer for cursor1 image. note these bits will not effective until the cursor1 enable bit is set to 1 (reg[c0h] bit 7=1). cursor1 position x register 0 reg[d0h] bit 7 6 5 4 3 2 1 0 cursor1 position x bit 7 cursor1 position x bit 6 cursor1 position x bit 5 cursor1 position x bit 4 cursor1 position x bit 3 cursor1 position x bit 2 cursor1 position x bit 1 cursor1 position x bit 0 type rw rw rw rw rw rw rw rw reset state 0 0 0 0 0 0 0 0 cursor1 position x register 1 reg[d1h] bit 7 6 5 4 3 2 1 0 0 0 0 0 0 0 cursor1 position x bit 9 cursor1 position x bit 8 type na na na na na na rw rw reset state 0 0 0 0 0 0 0 0 reg[d1h] bits 1-0, reg[d0h] bits 7-0 cursor1 position x bits [9:0] this is starting position x of cursor1 image. the definition of this register is same as floating window start position x register. note these bits will not effective until the cursor1 enable bit is set to 1 (reg[c0h] bit 7=1). cursor1 position y register 0 reg[d4h] bit 7 6 5 4 3 2 1 0 cursor1 position y bit 7 cursor1 position y bit 6 cursor1 position y bit 5 cursor1 position y bit 4 cursor1 position y bit 3 cursor1 position y bit 2 cursor1 position y bit 1 cursor1 position y bit 0 type rw rw rw rw rw rw rw rw reset state 0 0 0 0 0 0 0 0 cursor1 position y register 1 reg[d5h] bit 7 6 5 4 3 2 1 0 0 0 0 0 0 0 cursor1 position y bit 9 cursor1 position y bit 8 type na na na na na na rw rw reset state 0 0 0 0 0 0 0 0 reg[d5h] bits 1-0, reg[d4h] bits 7-0 cursor1 position y bits [9:0] this is starting position y of cursor1 image. the definition of this register is same as floating window y start position register. note these bits will not effective until the cursor1 enable bit is set to 1 (reg[c0h] bit 7=1).
solomon rev 1.3 10/2002 ssd1905 52 cursor1 horizontal size register reg[d8h] bit 7 6 5 4 3 2 1 0 0 0 0 cursor1 horizontal size bit 4 cursor1 horizontal size bit 3 cursor1 horizontal size bit 2 cursor1 horizontal size bit 1 cursor1 horizontal size bit 0 type na na na rw rw rw rw rw reset state 0 0 0 0 0 0 0 0 bits 4-0 cursor1 horizontal size bits [4:0] these bits specify the horizontal size of cursor1. note : the definition of this register various under different panel orientation and color depth settings. these bits will not effective until the cursor1 enable bit is set to 1 (reg[c0h] bit 7=1). table 7-19 : x increment mode for various color depths orientation color depths (bpp) increment (x) 4 8 0 ? 16 16 pixel increment e.g. 00000b = 16 pixel; 00001b = 32 pixel 4 2 line increment 8 4 line increment 90 ? 16 8 line increment 4 8 180 ? 16 16 pixel increment 4 2 line increment 8 4 line increment 270 ? 16 8 line increment cursor1 vertical size register reg[dch] bit 7 6 5 4 3 2 1 0 0 0 0 cursor1 vertical size bit 4 cursor1 vertical size bit 3 cursor1 vertical size bit 2 cursor1 vertical size bit 1 cursor1 vertical size bit 0 type na na na rw rw rw rw rw reset state 0 0 0 0 0 0 0 0 bits 4-0 cursor1 vertical size bits [4:0] these bits specify the vertical size of cursor1. note the definition of this register various under different panel orientation and color depth settings. these bits will not effective until the cursor1 enable bit is set to 1 (reg[c0h] bit 7=1).
ssd1905 rev 1.3 10/2002 solomon 53 table 7-20 : y increment mode for various color depths orientation color depths (bpp) increment (y) 4 8 0 ? 16 1 line increment e.g. 00000b = 1 line; 00001b = 2 lines 4 8 pixel increment 8 4 pixel increment 90 ? 16 2 pixel increment 4 8 180 ? 16 1 line increment 4 8 pixel increment 8 4 pixel increment 270 ? 16 2 pixel increment cursor1 color index1 register 0 reg[e0h] bit 7 6 5 4 3 2 1 0 cursor1 color index1 bit 7 cursor1 color index1 bit 6 cursor1 color index1 bit 5 cursor1 color index1 bit 4 cursor1 color index1 bit 3 cursor1 color index1 bit 2 cursor1 color index1 bit 1 cursor1 color index1 bit 0 type rw rw rw rw rw rw rw rw reset state 0 0 0 0 0 0 0 0 cursor1 color index1 register 1 reg[e1h] bit 7 6 5 4 3 2 1 0 cursor1 color index1 bit 15 cursor1 color index1 bit 14 cursor1 color index1 bit 13 cursor1 color index1 bit 12 cursor1 color index1 bit 11 cursor1 color index1 bit 10 cursor1 color index1 bit 9 cursor1 color index1 bit 8 type rw rw rw rw rw rw rw rw reset state 0 0 0 0 0 0 0 0 reg[e1h] bits 7-0, reg[e0h] bits 7-0 cursor1 color index1 bits [15:0] each cursor pixel is represented by 2 bits. this register stores the color index for pixel value 01 of cursor1, refer to table 20-1. note these bits will not effective until the cursor1 enable bit is set to 1 (reg[c0h] bit 7=1). for hardware cursors operation, see section 20 ?hardware cursor mode?. cursor1 color index2 register 0 reg[e4h] bit 7 6 5 4 3 2 1 0 cursor1 color index2 bit 7 cursor1 color index2 bit 6 cursor1 color index2 bit 5 cursor1 color index2 bit 4 cursor1 color index2 bit 3 cursor1 color index2 bit 2 cursor1 color index2 bit 1 cursor1 color index2 bit 0 type rw rw rw rw rw rw rw rw reset state 0 0 0 0 0 0 0 0
solomon rev 1.3 10/2002 ssd1905 54 cursor1 color index2 register 1 reg[e5h] bit 7 6 5 4 3 2 1 0 cursor1 color index2 bit 15 cursor1 color index2 bit 14 cursor1 color index2 bit 13 cursor1 color index2 bit 12 cursor1 color index2 bit 11 cursor1 color index2 bit 10 cursor1 color index2 bit 9 cursor1 color index2 bit 8 type rw rw rw rw rw rw rw rw reset state 0 0 0 0 0 0 0 0 reg[e5h] bits 7-0, reg[e4h] bits 7-0 cursor1 color index2 bits [15:0] each cursor pixel is represented by 2 bits. this register stores the color index for pixel value 10 of cursor1, refer to table 20-1. note these bits will not effective until the cursor1 enable bit is set to 1 (reg[c0h] bit 7=1). for hardware cursors operation, see section 20 ?hardware cursor mode?. cursor1 color index3 register 0 reg[e8h] bit 7 6 5 4 3 2 1 0 cursor1 color index3 bit 7 cursor1 color index3 bit 6 cursor1 color index3 bit 5 cursor1 color index3 bit 4 cursor1 color index3 bit 3 cursor1 color index3 bit 2 cursor1 color index3 bit 1 cursor1 color index3 bit 0 type rw rw rw rw rw rw rw rw reset state 0 0 0 0 0 0 0 0 cursor1 color index3 register 1 reg[e9h] bit 7 6 5 4 3 2 1 0 cursor1 color index3 bit 15 cursor1 color index3 bit 14 cursor1 color index3 bit 13 cursor1 color index3 bit 12 cursor1 color index3 bit 11 cursor1 color index3 bit 10 cursor1 color index3 bit 9 cursor1 color index3 bit 8 type rw rw rw rw rw rw rw rw reset state 0 0 0 0 0 0 0 0 reg[e9h] bits 7-0, reg[e8h] bits 7-0 cursor1 color index3 bits [15:0] each cursor pixel is represented by 2 bits. this register stores the color index for pixel value 11 of cursor1, refer to table 20-1. note these bits will not effective until the cursor1 enable bit is set to 1 (reg[c0h] bit 7=1). for hardware cursors operation, see section 20 ?hardware cursor mode?. cursor2 blink total register 0 reg[ech] bit 7 6 5 4 3 2 1 0 cursor2 blink total bit 7 cursor2 blink total bit 6 cursor2 blink total bit 5 cursor2 blink total bit 4 cursor2 blink total bit 3 cursor2 blink total bit 2 cursor2 blink total bit 1 cursor2 blink total bit 0 type rw rw rw rw rw rw rw rw reset state 0 0 0 0 0 0 0 0
ssd1905 rev 1.3 10/2002 solomon 55 cursor2 blink total register 1 reg[edh] bit 7 6 5 4 3 2 1 0 0 0 0 0 0 0 cursor2 blink total bit 9 cursor2 blink total bit 8 type na na na na na na rw rw reset state 0 0 0 0 0 0 0 0 reg[edh] bits 1-0, reg[ech] bits 7-0 cursor2 blink total bits [9:0] this is the total blinking period per frame for cursor2. this register must be set to a non-zero value in order to make the cursor visible. note these bits will not effective until the cursor2 enable bit is set to 1 (reg[c0h] bit 6=1). cursor2 blink on register 0 reg[f0h] bit 7 6 5 4 3 2 1 0 cursor2 blink on bit 7 cursor2 blink on bit 6 cursor2 blink on bit 5 cursor2 blink on bit 4 cursor2 blink on bit 3 cursor2 blink on bit 2 cursor2 blink on bit 1 cursor2 blink on bit 0 type rw rw rw rw rw rw rw rw reset state 0 0 0 0 0 0 0 0 cursor2 blink on register 1 reg[f1h] bit 7 6 5 4 3 2 1 0 0 0 0 0 0 0 cursor2 blink on bit 9 cursor2 blink on bit 8 type na na na na na na rw rw reset state 0 0 0 0 0 0 0 0 reg[f1h] bits 1-0, reg[f0h] bits 7-0 cursor2 blink on bits [9:0] this is the blink on frame period for cursor2. this register must be set to a non-zero value in order to make the cursor2 visible. also, cursor2 will start to blink if the following conditions are fulfilled: cursor2 blink total bits [9:0] > cursor2 blink on bits [9:0] > 0 note to enable cursor2 without blinking, user must program cursor2 blink on register with a non-zero value, and this value must be greater than or equal to cursor2 blink total register. these bits will not effective until the cursor2 enable bit is set to 1 (reg[c0h] bit 6=1). cursor2 memory start register 0 reg[f4h] bit 7 6 5 4 3 2 1 0 cursor2 memory start bit 7 cursor2 memory start bit 6 cursor2 memory start bit 5 cursor2 memory start bit 4 cursor2 memory start bit 3 cursor2 memory start bit 2 cursor2 memory start bit 1 cursor2 memory start bit 0 type rw rw rw rw rw rw rw rw reset state 0 0 0 0 0 0 0 0
solomon rev 1.3 10/2002 ssd1905 56 cursor2 memory start register 1 reg[f5h] bit 7 6 5 4 3 2 1 0 cursor2 memory start bit 15 cursor2 memory start bit 14 cursor2 memory start bit 13 cursor2 memory start bit 12 cursor2 memory start bit 11 cursor2 memory start bit 10 cursor2 memory start bit 9 cursor2 memory start bit 8 type rw rw rw rw rw rw rw rw reset state 0 0 0 0 0 0 0 0 cursor2 memory start register 2 reg[f6h] bit 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 cursor2 memory start bit 16 type na na na na na na na rw reset state 0 0 0 0 0 0 0 0 reg[f6h] bit 0, reg[f5h] bits 7-0, reg[f4h] bits 7-0 cursor2 memory start bits [16:0] this is the start location of memory buffer for cursor2 image. note these bits will not effective until the cursor2 enable bit is set to 1 (reg[c0h] bit 6=1). cursor2 position x register 0 reg[f8h] bit 7 6 5 4 3 2 1 0 cursor2 position x bit 7 cursor2 position x bit 6 cursor2 position x bit 5 cursor2 position x bit 4 cursor2 position x bit 3 cursor2 position x bit 2 cursor2 position x bit 1 cursor2 position x bit 0 type rw rw rw rw rw rw rw rw reset state 0 0 0 0 0 0 0 0 cursor2 position x register 1 reg[f9h] bit 7 6 5 4 3 2 1 0 0 0 0 0 0 0 cursor2 position x bit 9 cursor2 position x bit 8 type na na na na na na rw rw reset state 0 0 0 0 0 0 0 0 reg[f9h] bits 1-0, reg[f8h] bits 7-0 cursor2 position x bits [9:0] this is starting position x of cursor2 image. the definition of this register is same as floating window start position x register. note these bits will not effective until the cursor2 enable bit is set to 1 (reg[c0h] bit 6=1). cursor2 position y register 0 reg[fch] bit 7 6 5 4 3 2 1 0 cursor2 position y bit 7 cursor2 position y bit 6 cursor2 position y bit 5 cursor2 position y bit 4 cursor2 position y bit 3 cursor2 position y bit 2 cursor2 position y bit 1 cursor2 position y bit 0 type rw rw rw rw rw rw rw rw reset state 0 0 0 0 0 0 0 0
ssd1905 rev 1.3 10/2002 solomon 57 cursor2 position y register 1 reg[fdh] bit 7 6 5 4 3 2 1 0 0 0 0 0 0 0 cursor2 position y bit 9 cursor2 position y bit 8 type na na na na na na rw rw reset state 0 0 0 0 0 0 0 0 reg[fdh] bits 1-0, reg[fch] bits 7-0 cursor2 position y bits [9:0] this is starting position y of cursor2 image. the definition of this register is same as floating window y start position register. note these bits will not effective until the cursor2 enable bit is set to 1 (reg[c0h] bit 6=1). cursor2 horizontal size register reg[100h] bit 7 6 5 4 3 2 1 0 0 0 0 cursor2 horizontal size bit 4 cursor2 horizontal size bit 3 cursor2 horizontal size bit 2 cursor2 horizontal size bit 1 cursor2 horizontal size bit 0 type na na na rw rw rw rw rw reset state 0 0 0 0 0 0 0 0 bits 4-0 cursor2 horizontal size bits [4:0] these bits specify the horizontal size of cursor2. note : the definition of this register various under different panel orientation and color depth settings. refer to table 7-19 : x increment mode for various color depths. these bits will not effective until the cursor2 enable bit is set to 1 (reg[c0h] bit 6=1). cursor2 vertical size register reg[104h] bit 7 6 5 4 3 2 1 0 0 0 0 cursor2 vertical size bit 4 cursor2 vertical size bit 3 cursor2 vertical size bit 2 cursor2 vertical size bit 1 cursor2 vertical size bit 0 type na na na rw rw rw rw rw reset state 0 0 0 0 0 0 0 0 bits 4-0 cursor2 vertical size bits [4:0] these bits specify the vertical size of cursor2. note : the definition of this register various under different panel orientation and color depth settings. refer to table 7-20 : y increment mode for various color depths. these bits will not effective until the cursor2 enable bit is set to 1 (reg[c0h] bit 6=1).
solomon rev 1.3 10/2002 ssd1905 58 cursor2 color index1 register 0 reg[108h] bit 7 6 5 4 3 2 1 0 cursor2 color index1 bit 7 cursor2 color index1 bit 6 cursor2 color index1 bit 5 cursor2 color index1 bit 4 cursor2 color index1 bit 3 cursor2 color index1 bit 2 cursor2 color index1 bit 1 cursor2 color index1 bit 0 type rw rw rw rw rw rw rw rw reset state 0 0 0 0 0 0 0 0 cursor2 color index1 register 1 reg[109h] bit 7 6 5 4 3 2 1 0 cursor2 color index1 bit 15 cursor2 color index1 bit 14 cursor2 color index1 bit 13 cursor2 color index1 bit 12 cursor2 color index1 bit 11 cursor2 color index1 bit 10 cursor2 color index1 bit 9 cursor2 color index1 bit 8 type rw rw rw rw rw rw rw rw reset state 0 0 0 0 0 0 0 0 reg[109h] bits 7-0 reg[108h] bits 7-0 cursor2 color index1 bits [15:0] each cursor pixel is represented by 2 bits. this register stores the color index for pixel value 01 of cursor2, refer to table 20-1. note these bits will not effective until the cursor2 enable bit is set to 1 (reg[c0h] bit 6=1). for hardware cursors operation, see section 20 ?hardware cursor mode?. cursor2 color index2 register 0 reg[10ch] bit 7 6 5 4 3 2 1 0 cursor2 color index2 bit 7 cursor2 color index2 bit 6 cursor2 color index2 bit 5 cursor2 color index2 bit 4 cursor2 color index2 bit 3 cursor2 color index2 bit 2 cursor2 color index2 bit 1 cursor2 color index2 bit 0 type rw rw rw rw rw rw rw rw reset state 0 0 0 0 0 0 0 0 cursor2 color index2 register 1 reg[10dh] bit 7 6 5 4 3 2 1 0 cursor2 color index2 bit 15 cursor2 color index2 bit 14 cursor2 color index2 bit 13 cursor2 color index2 bit 12 cursor2 color index2 bit 11 cursor2 color index2 bit 10 cursor2 color index2 bit 9 cursor2 color index2 bit 8 type rw rw rw rw rw rw rw rw reset state 0 0 0 0 0 0 0 0 reg[10dh] bits 7-0 reg[10ch] bits 7-0 cursor2 color index2 bits [15:0] each cursor pixel is represented by 2 bits. this register stores the color index for pixel value 10 of cursor2, refer to table 20-1. note these bits will not effective until the cursor2 enable bit is set to 1 (reg[c0h] bit 6=1). for hardware cursors operation, see section 20 ?hardware cursor mode?.
ssd1905 rev 1.3 10/2002 solomon 59 cursor2 color index3 register 0 reg[110h] bit 7 6 5 4 3 2 1 0 cursor2 color index3 bit 7 cursor2 color index3 bit 6 cursor2 color index3 bit 5 cursor2 color index3 bit 4 cursor2 color index3 bit 3 cursor2 color index3 bit 2 cursor2 color index3 bit 1 cursor2 color index3 bit 0 type rw rw rw rw rw rw rw rw reset state 0 0 0 0 0 0 0 0 cursor2 color index3 register 1 reg[111h] bit 7 6 5 4 3 2 1 0 cursor2 color index3 bit 15 cursor2 color index3 bit 14 cursor2 color index3 bit 13 cursor2 color index3 bit 12 cursor2 color index3 bit 11 cursor2 color index3 bit 10 cursor2 color index3 bit 9 cursor2 color index3 bit 8 type rw rw rw rw rw rw rw rw reset state 0 0 0 0 0 0 0 0 reg[111h] bits 7-0 reg[110h] bits 7-0 cursor2 color index3 bits [15:0] each cursor pixel is represented by 2 bits. this register stores the color index for pixel value 11 of cursor2, refer to table 20-1. note these bits will not effective until the cursor2 enable bit is set to 1 (reg[c0h] bit 6=1). for hardware cursors operation, see section 20 ?hardware cursor mode?.
solomon rev 1.3 10/2002 ssd1905 60 8 maximum ratings table 8-1 : absolute maximum ratings symbol parameter rating units iov dd supply voltage v ss - 0.3 to 4.0 v v in input voltage v ss - 0.3 to 5.0 v v out output voltage v ss - 0.3 to iov dd + 0.5 v t stg storage temperature -65 to 150 c t sol solder temperature/time 260 for 10 sec. max at lead c maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the limits in the electrical characteristics tables or pin description section. this device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions to be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. for proper operation it is recommended that v in and v out be constrained to the range v ss (v in or v out ) iov dd . reliability of operation is enhanced if unused input are connected to an appropriate logic voltage level (e.g., either v ss or iov dd ). this device is not radiation protected. table 8-2 : recommended operating conditions symbol parameter condition min typ max units iov dd supply voltage v ss = 0v 3.0 3.3 3.6 v v in input voltage v ss iov dd v t opr operating temperature -30 25 85 c
ssd1905 rev 1.3 10/2002 solomon 61 9 dc characteristics table 9-1 : electrical characteristics for iov dd = 3.3v typical symbol parameter condition min typ max units i dds quiescent current quiescent conditions 120 a i iz input leakage current -1 1 a i oz output leakage current -1 1 a v oh high level output voltage iov dd = min i oh = -8ma (type 2) -12ma (type 3) iov dd -0.4 v v ol low level output voltage iov dd = min i ol = 8ma (type2) 12ma (type 3) 0.4 v v ih high level input voltage lvttl level, iov dd = max iov dd -0.8 v v il low level input voltage lvttl level, iov dd = min 0.8 v v t+ high level input voltage lvttl schmitt 1.1 v v t- low level input voltage lvttl schmitt 0.94 v v h1 hysteresis voltage lvttl schmitt 0.15 v c i input pin capacitance 10 pf c o output pin capacitance 10 pf c io bi-directional pin capacitance 10 pf 10 ac characteristics conditions: iov dd = 3.3v 10% t a =-30 c to 85 c t rise and t fall for all inputs must be < 5 ns (10% ~ 90%) c l = 50pf (bus/cpu interface) c l = 0pf (lcd panel interface)
solomon rev 1.3 10/2002 ssd1905 62 10.1 clock timing 10.1.1 input clocks 90% vih vil 10% t osc t pwl t pwh t f t r clock input waveform figure 10-1 : clock input requirements table 10-1 : clock input requirements for clki symbol parameter min max units f osc input clock frequency (clki) 66 mhz t osc input clock period (clki) 1/f osc ns t pwh input clock pulse width high (clki) 5 ns t pwl input clock pulse width low (clki) 5 ns t f input clock fall time (10% - 90%) 5 ns t r input clock rise time (10% - 90%) 5 ns note maximum internal requirements for clocks derived from clki must be considered when determining the frequency of clki. see section 10.1.2 ?internal clocks? for internal clock requirements.
ssd1905 rev 1.3 10/2002 solomon 63 table 10-2 : clock input requirements for auxclk symbol parameter min max units f osc input clock frequency (auxclk) 66 mhz t osc input clock period (auxclk) 1/f osc ns t pwh input clock pulse width high (auxclk) 5 ns t pwl input clock pulse width low (auxclk) 5 ns t f input clock fall time (10% - 90%) 5 ns t r input clock rise time (10% - 90%) 5 ns note : maximum internal requirements for clocks derived from auxclk must be considered when determining the frequency of auxclk. see section 10.1.2 ?internal clocks? for internal clock requirements. 10.1.2 internal clocks table 10-3 : internal clock requirements symbol parameter min max units f bclk bus clock frequency 66 mhz f mclk memory clock frequency 55 mhz f pclk pixel clock frequency 55 mhz f pwmclk pwm clock frequency 66 mhz note : for further information on internal clocks, refer to section 11 ?clocks?.
solomon rev 1.3 10/2002 ssd1905 64 10.2 cpu interface timing the following section are cpu interface ac timing based on iov dd = 3.3v. 10.2.1 generic #1 interface timing t 13 t 7 t 9 a[16:1], m/r#, t 10 clk wait# rd0#, rd1# we0#, we1# cs# d[15:0] (read) d[15:0] (write) t clk t 2 t 1 t 3 t 4 t 6 t 5 t 15 t 11 t 14 t 12 t 8 valid figure 10-2 : generic #1 interface timing
ssd1905 rev 1.3 10/2002 solomon 65 table 10-4 : generic #1 interface timing symbol parameter min max units f clk bus clock frequency 66 mhz t clk bus clock period 1/f clk ns t 1 clock pulse width high 6 ns t 2 clock pulse width low 6 ns t 3 a[16:1], m/r# setup to first clk rising edge where cs# = 0 and either rd0#, rd1# = 0 or we0#, we1# = 0 1 ns t 4 a[16:1], m/r# hold from either rd0#, rd1# or we0#, we1# rising edge 0 ns t 5 cs# setup to clk rising edge 1 ns t 6 cs# hold from either rd0#, rd1# or we0#, we1# rising edge 1 ns t 7a rd0#, rd1#, we0#, we1# asserted for mclk = bclk 13 t clk t 7b rd0#, rd1#, we0#, we1# asserted for mclk = bclk 2 18 t clk t 7c rd0#, rd1#, we0#, we1# asserted for mclk = bclk 3 23 t clk t 7d rd0#, rd1#, we0#, we1# asserted for mclk = bclk 4 28 t clk t 8 rd0#, rd1#, we0#, we1# setup to clk rising edge 1 ns t 9 falling edge of either rd0#, rd1# or we0#, we1# to wait# driven low 3 15 ns t 10 rising edge of either rd0#, rd1# or we0#, we1# to wait# high impedance 3 13 ns t 11 d[15:0] setup to third clk rising edge where cs# = 0 and we0#,we1#=0 (write cycle)(see note1) 0 ns t 12 d[15:0] hold from wait# rising edge (write cycle) 0 ns t 13 rd0#, rd1# falling edge to d[15:0] driven (read cycle) 3 14 ns t 14 wait# rising edge to d[15:0] valid (read cycle) 2 ns t 15 rd0#, rd1# rising edge to d[15:0] high impedance (read cycle) 3 11 ns 1. t 11 is the delay from when data is placed on the bus until the data is latched into the write buffer.
solomon rev 1.3 10/2002 ssd1905 66 10.2.2 generic #2 interface timing (e.g. isa) t 13 t 7 t 9 sa[16:0], m/r#, sbhe# t 10 busclk iochrdy memr# memw # cs# sd[15:0] (read) sd[15:0] (write) t busclk t 2 t 1 t 3 t 4 t 6 t 5 t 15 t 11 t 14 t 12 t 8 valid figure 10-3 : generic #2 interface timing
ssd1905 rev 1.3 10/2002 solomon 67 table 10-5 : generic #2 interface timing symbol parameter min max units f busclk bus clock frequency 66 mhz t busclk bus clock period 1/f busclk ns t 1 clock pulse width high 6 ns t 2 clock pulse width low 6 ns t 3 sa[16:0], m/r#, sbhe# setup to first busclk rising edge where cs# = 0 and either memr# = 0 or memw# = 0 1 ns t 4 sa[16:0], m/r#, sbhe# hold from either memr# or memw# rising edge 0 ns t 5 cs# setup to busclk rising edge 1 ns t 6 cs# hold from either memr# or memw# rising edge 0 ns t 7a memr# or memw# asserted for mclk = bclk 13 t busclk t 7b memr# or memw# asserted for mclk = bclk 2 18 t busclk t 7c memr# or memw# asserted for mclk = bclk 3 23 t busclk t 7d memr# or memw# asserted for mclk = bclk 4 28 t busclk t 8 memr# or memw# setup to busclk rising edge 1 ns t 9 falling edge of either memr# or memw# to iochrdy driven low 3 15 ns t 10 rising edge of either memr# or memw# to iochrdy high impedance 3 13 ns t 11 sd[15:0] setup to third busclk rising edge where cs# = 0 and memw#=0 (write cycle)(see note1) 0 ns t 12 sd[15:0] hold from iochrdy rising edge (write cycle) 0 ns t 13 memr# falling edge to sd[15:0] driven (read cycle) 3 13 ns t 14 iochrdy rising edge to sd[15:0] valid (read cycle) 2 ns t 15 rising edge of memr# to sd[15:0] high impedance (read cycle) 3 12 ns 1. t 11 is the delay from when data is placed on the bus until the data is latched into the write buffer.
solomon rev 1.3 10/2002 ssd1905 68 10.2.3 motorola mc68k #1 interface timing (e.g. mc68000) t 19 t 7 t 20 t 11 t 9 a[16 : 1] , m/ r# uds# , lds# t 10 clk dta c k # r/w# as# cs # d[15:0] (w r ite) t clk t 2 t 1 t 3 t 4 t 6 t 5 t 15 t 17 t 18 t 14 t 12 t 13 t 16 t 8 d[15:0] (read) t 21 vali d figure 10-4 : motorola mc68k #1 interface timing
ssd1905 rev 1.3 10/2002 solomon 69 table 10-6 : motorola mc68k #1 interface timing symbol parameter min max units f clk bus clock frequency 66 mhz t clk bus clock period 1/f clk ns t 1 clock pulse width high 6 ns t 2 clock pulse width low 6 ns t 3 a[16:1], m/r# setup to first clk rising edge where cs# = 0, as#=0,uds#=0,and lds#=0 1 ns t 4 a[16:1], m/r# hold from as# rising edge 0 ns t 5 cs# setup to clk rising edge while as#, uds#/lds# = 0 1 ns t 6 cs# hold from as# rising edge 0 ns t 7a as# asserted for mclk = bclk 13 t clk t 7b as# asserted for mclk = bclk 2 18 t clk t 7c as# asserted for mclk = bclk 3 23 t clk t 7d as# asserted for mclk = bclk 4 28 t clk t 8 as# setup to clk rising edge while cs#, as#, uds#/lds# =0 1 ns t 9 as# setup to clk rising edge 2 t clk t 10 uds#/lds# setup to clk rising edge while cs#, as#, uds#/lds# = 0 1 ns t 11 uds#/lds# high setup to clk rising edge 2 ns t 12 first clk rising edge where as#=1 to dtack# high impedance 3 14 ns t 13 r/w# setup to clk rising edge before all cs#, as#, uds# and/or lds# = 0 1 ns t 14 r/w# hold from as# rising edge 0 ns t 15 as# = 0 and cs# = 0 to dtack# driven high 3 13 ns t 16 as# rising edge to dtack# rising edge 4 16 ns t 17 d[15:0] valid to third clk rising edge where cs# = 0, as# = 0 and either uds# = 0 or lds# = 0 (write cycle) (see note 1) 0 ns t 18 d[15:0] hold from dtack# falling edge (write cycle) 0 ns t 19 uds# = 0 and/or lds# = 0 to d[15:0] driven (read cycle) 3 13 ns t 20 dtack# falling edge to d[15:0] valid (read cycle) 2 ns t 21 uds#, lds# rising edge to d[15:0] high impedance (read cycle) 3 13 ns 1. t 17 is the delay from when data is placed on the bus until the data is latched into the write buffer.
solomon rev 1.3 10/2002 ssd1905 70 10.2.4 motorola dragonball interface timing with dtack# (e.g. mc68ez328/mc68vz328) t 3 t 4 t 5 uw e #/ lwe # (w rite) t 2 t clko t 1 t 19 t 7 t 11 t 9 o e # (read) t 10 dta ck# d[15:0] (read) d[15:0] (w rite) t 6 t 15 t 17 t 18 t 14 t 12 t 13 t 16 t 8 va lid hi- z hi- z a [16:1] hi - z hi- z csx# clko figure 10-5 : motorola dragonball interface with dtack# timing
ssd1905 rev 1.3 10/2002 solomon 71 table 10-7 : motorola dragonball interface with dtack# timing symbol parameter mc68ez328 mc68vz328 units min max min max f clko bus clock frequency 16 33 mhz t clko bus clock period 1/f clko 1/f clko ns t 1 clock pulse width high 28.1 13.5 ns t 2 clock pulse width low 28.1 13.5 ns t 3 a[16:1] setup 1st clko when csx# = 0 and either uwe#/lwe# or oe# =0 0 0 ns t 4 a[16:1] hold from csx# rising edge 0 0 ns t 5a csx# asserted for mclk = bclk 13 13 t clko t 5b csx# asserted for mclk = bclk 2 18 18 t clko t 5c csx# asserted for mclk = bclk 3 23 23 t clko t 5d csx# asserted for mclk = bclk 4 28 28 t clko t 6 csx# setup to clko rising edge 0 0 ns t 7 csx# rising edge to clko rising edge 0 0 ns t 8 uwe#/lwe# falling edge to clko rising edge 0 0 ns t 9 uwe#/lwe# rising edge to csx# rising edge 0 0 ns t 10 oe# falling edge to clko rising edge 1 1 ns t 11 oe# hold from csx# rising edge 0 0 ns t 12 d[15:0] setup to 3rd clko when csx#, uwe#/lwe# asserted (write cycle) (see note 1) 0 0 ns t 13 d[15:0] in hold from csx# rising edge(write cycle) 0 0 ns t 14 falling edge of oe# to d[15:0] driven (read cycle) 3 15 3 15 ns t 15 clko rising edge to d[15:0] output hi-z (read cycle) 2 12 2 12 ns t 16 csx# falling edge to dtack# driven high 3 13 3 13 ns t 17 dtack# falling edge to d[15:0]valid (read cycle) 2 2 ns t 18 csx# high to dtack# high 3 16 3 16 ns t 19 clko rising edge to dtack# hi-z 1 6 1 6 ns 1 t 12 is the delay from when data is placed on the bus until the data is latched into the write buffer.
solomon rev 1.3 10/2002 ssd1905 72 10.2.5 motorola dragonball interface timing without dtack# (e.g. mc68ez328/mc68vz328) figure 10-6 : motorola dragonball interface without dtack# timing t 15 t 14 t 10 t 3 t 4 t 5 uwe#/lwe# ( write ) t 2 clko t clko t 1 t 7 t 11 t 9 oe# (read) d[15:0] (read) d[15:0] (write) t 6 t 12 t 13 t 16 t 8 valid hi-z hi-z a [16:1] hi-z hi-z csx #
ssd1905 rev 1.3 10/2002 solomon 73 table 10-8 : motorola dragonball interface without dtack# timing symbol parameter mc68ez328 mc68vz328 units min max min max f clko bus clock frequency 16 33 mhz t clko bus clock period 1/f clko 1/f clko ns t 1 clock pulse width high 28.1 13.6 ns t 2 clock pulse width low 28.1 13.6 ns t 3 a[16:1] setup 1st clko when csx# = 0 and either uwe#/lwe# or oe# =0 0 0 ns t 4 a[16:1] hold from csx# rising edge 0 0 ns t 5a csx# asserted for mclk = bclk 13 13 t clko t 5b csx# asserted for mclk = bclk 2 18 18 t clko t 5c csx# asserted for mclk = bclk 3 23 23 t clko t 5d csx# asserted for mclk = bclk 4 28 28 t clko t 6 csx# setup to clko rising edge 0 0 ns t 7 csx# rising edge to clko rising edge 0 0 ns t 8 uwe#/lwe# falling edge to clko rising edge 0 0 ns t 9 uwe#/lwe# rising edge to csx# rising edge 0 0 ns t 10 oe# falling edge to clko rising edge 1 1 ns t 11 oe# hold from csx# rising edge 0 0 ns t 12 d[15:0] setup to 3rd clko when csx#, uwe#/lwe# asserted (write cycle) (see note 1) 0 0 ns t 13 d[15:0] hold from csx# rising edge(write cycle) 0 0 ns t 14 falling edge of oe# to d[15:0] driven (read cycle) 3 15 3 15 ns t 15a 1st clko rising edge after oe# and csx# asserted low to d[15:0] valid for mclk = bclk (read cycle) 13 13 t clko t 15b 1st clko rising edge after oe# and csx# asserted low to d[15:0] valid for mclk = bclk 2 (read cycle) 18 18 t clko t 15c 1st clko rising edge after oe# and csx# asserted low to d[15:0] valid for mclk = bclk 3 (read cycle) 23 23 t clko t 15d 1st clko rising edge after oe# and csx# asserted low to d[15:0] valid for mclk = bclk 4 (read cycle) 28 28 t clko t 16 clko rising edge to d[15:0] output hi-z (read cycle) 2 12 2 12 ns note 1 t 12 is the delay from when data is placed on the bus until the data is latched into the write buffer.
solomon rev 1.3 10/2002 ssd1905 74 t 9 a[16:1], m/r#, rd/wr# hi-z t 10 ckio wait# wen#, rd# csn# bs# d[15:0] (read) d[15:0] (write) t ckio t 2 t 1 t 3 t 4 t 6 t 5 t 15 t 11 t 17 t 14 t 12 t 13 t 16 t 8 hi-z hi-z hi-z hi-z hi-z t 7 valid 10.2.6 hitachi sh-3 interface timing (e.g. sh7709a) figure 10-7 : hitachi sh-3 interface timing
ssd1905 rev 1.3 10/2002 solomon 75 table 10-9 : hitachi sh-3 interface timing symbol parameter min max units f ckio bus clock frequency 66 mhz t ckio bus clock period 1/f ckio ns t 1 bus clock pulse width low 9 ns t 2 bus clock pulse width high 9 ns t 3 a[16:1], m/r#, rd/wr# setup to ckio 1 ns t 4 csn# high setup to ckio 1 ns t 5 bs# setup 1 ns t 6 bs# hold 2 ns t 7 csn# setup 1 ns t 8 a[16:1], m/r#, rd/wr# hold from cs# 0 ns t 9a rd# or wen# asserted for mclk = bclk (max.mclk=50mhz) 13 t ckio t 9b rd# or wen# asserted for mclk = bclk 2 18 t ckio t 9c rd# or wen# asserted for mclk = bclk 3 23 t ckio t 9d rd# or wen# asserted for mclk = bclk 4 28 t ckio t 10 falling edge rd# to d[15:0] driven (read cycle) 3 12 ns t 11 rising edge csn# to wait# high impedance 2 10 ns t 12 falling edge csn# to wait# driven low 3t ckio + 2 3t ckio + 12 ns t 13 clio to wait# delay 4 18 ns t 14 d[15:0] setup to 2 nd ckio after bs# (write cycle) (see note 1) 0 ns t 15 d[15:0] hold (write cycle) 0 ns t 16 wait# rising edge to d[15:0] valid (read cycle) 2 ns t 17 rising edge rd# to d[15:0] high impedance (read cycle) 3 12 ns 1. t 14 is the delay from when data is placed on the bus until the data is latched into the write buffer. note minimum three software wait state are required.
solomon rev 1.3 10/2002 ssd1905 76 10.2.7 hitachi sh-4 interface timing (e.g. sh7751) figure 10-8 : hitachi sh-4 interface timing t 9 a [16:1], m/r#, rd/wr# hi - z t 10 ckio rdy# wen#, rd# csn# bs# d[15:0] (read) d[15:0] (write) t ckio t 2 t 1 t 3 t 4 t 6 t 5 t 15 t 11 t 17 t 18 t 14 t 12 t 13 t 16 t 8 hi - z hi - z hi - z hi - z hi - z t 7 valid
ssd1905 rev 1.3 10/2002 solomon 77 table 10-10 : hitachi sh-4 interface timing symbol parameter min max units f ckio clock frequency 66 mhz t ckio clock period 1/f ckio ns t 1 clock pulse width low 6.8 ns t 2 clock pulse width high 6.8 ns t 3 a[16:1], m/r#, rd/wr# setup to ckio 1 ns t 4 a[16:1], m/r#, rd/wr# hold from csn# 0 ns t 5 bs# setup 1 ns t 6 bs# hold 2 ns t 7 csn# setup 1 ns t 8 csn# high setup to ckio 2 ns t 9a rd# or wen# asserted for mclk = bclk (max.mclk=50mhz) 13 t ckio t 9b rd# or wen# asserted for mclk = bclk 2 18 t ckio t 9c rd# or wen# asserted for mclk = bclk 3 23 t ckio t 9d rd# or wen# asserted for mclk = bclk 4 28 t ckio t 10 falling edge rd# to d[15:0] driven (read cycle) 3 12 ns t 11 falling edge csn# to rdy# driven high 3t ckio + 3 3t ckio + 12 ns t 12 ckio to rdy# low 4 18 ns t 13 csn# high to rdy# high 4 14 ns t 14 falling edge ckio to rdy# high impedance 4 14 ns t 15 d[15:0] setup to 2 nd ckio after bs# (write cycle) (see note 1) 0 ns t 16 d[15:0] hold (write cycle) 0 ns t 17 rdy# falling edge to d[15:0] valid (read cycle) 2 ns t 18 rising edge rd# to d[15:0] high impedance (read cycle) 3 12 ns 1. t 15 is the delay from when data is placed on the bus until the data is latched into the write buffer. note minimum three software wait state are required.
solomon rev 1.3 10/2002 ssd1905 78 10.3 lcd power sequencing 10.3.1 passive/tft power-on sequence figure 10-9 : passive/tft power-on sequence timing table 10-11 : passive/tft power-on sequence timing symbol parameter min max units t 1 lcd signals active to lcd bias active note 1 note 1 t 2 power saving mode disabled to lcd signals active 0 20 ns 1. t 1 is controlled by software and must be determined from the bias power supply delay requirements of the panel connected. note for hr-tft power-on/off sequence information, see referenced document of sharp hr-tft panels. power saving mode enable** (reg[a0h] bit 0) lcd signals*** *it is recommended to use the general purpose output pin gpo to control the lcd bias power. **the lcd power-on sequence is activated by programming the power saving mode enable bit (reg[a0h] bit 0) to 0. ***lcd signal include: ldata[17:0], lshift, lline, lframe, and lden. gpo* t 2 t 1
ssd1905 rev 1.3 10/2002 solomon 79 10.3.2 passive/tft power-off sequence figure 10-10 : passive/tft power-off sequence timing table 10-12 : passive/tft power-off sequence timing symbol parameter min max units t 1 lcd bias deactivated active to lcd signals inactive note 1 note 1 t 2 power saving mode disabled to lcd signals low 0 20 ns 1. t 1 is controlled by software and must be determined from the bias power supply delay requirements of the panel connected. *it is recommended to use the general purpose output pin gpo to control the lcd bias power. **the lcd power-off sequence is activated by programming the power saving mode enable bit (reg[a0h] bit 0) to 1. ***lcd signal include: ldata[17:0], lshift, lline, lframe, and lden. power saving mode enable** (reg[a0h] bit 0) lcd signals*** gpo* t 2 t 1
solomon rev 1.3 10/2002 ssd1905 80 10.3.3 power saving status figure 10-11 : power saving status timing table 10-13 : power saving status timing symbol parameter min max units t 1 power saving mode disabled to memory controller power saving status low note 1 note 1 ns t 2 power saving mode enabled to memory controller power saving status high 0 20 mclk (note 1) 1. for further information on the internal clock mclk, see section11.1.2, ?mclk?. memory controller power saving status** power saving mode enable* ( reg [ a0h ] bit 0 ) t 2 t 1 * power saving mode is controlled by the power saving mode enable bit (reg[a0h] bit 0). ** memory controller power saving status is controlled by the memory controller power saving status bit (reg[a0h] bit3).
ssd1905 rev 1.3 10/2002 solomon 81 10.4 display interface figure 10-12 : panel timing parameters shows the timing parameters required to drive a flat panel display. timing details for each supported panel types are provided in the remainder of this section. figure 10-12 : panel timing parameters table 10-14 : panel timing parameter definition and register summary symbol description derived from units ht horizontal total ((reg[12h] bits 6-0) + 1) x 8 hdp 2 horizontal display period 2 ((reg[14h] bits 6-0) + 1) x 8 hdps 3 horizontal display period start position 3 ((reg[17h]bits1-0,reg[16h]bits7-0)+ offset 5 ) hps lline pulse start position (reg[23h] bits 1-0, reg[22h] bits 7-0) + 1 hpw lline pulse width (reg[20h] bits 6-0) + 1 ts 1 vt vertical total ((reg[19h] bits 1-0, reg[18h] bits 7-0) + 1) x ht vdp 4 vertical display period 4 ((reg[1dh] bits 1-0, reg[1ch] bits 7-0) + 1) x ht vdps vertical display period start position (reg[1fh] bits 1-0, reg[1eh] bits 7-0) x ht vps lframe pulse start position (reg[27h] bits 1-0, reg[26h] bits 7-0) x ht + (reg[31h] bits 1-0, reg[30h] bits 7-0) vpw lframe pulse width ((reg[24h] bits 2-0) + 1) x ht + (reg[35h] bits 1- 0, reg[34h] bits 7-0) ? (reg[31h] bits 1-0, reg[30h] bits 7-0) ts 1 hpw vt vdps hdps hdp ht hps vdp vps vpw
solomon rev 1.3 10/2002 ssd1905 82 the following conditions must be fulfilled for all panel timings: hdps + hdp < ht for passive lcd interface : vdps + vdp + 1 < vt for other lcd interface : vdps + vdp < vt 1 ts = pixel clock period 2 the hdp must be a minimum of 32 pixels and can be increased by multiples of 8. 3 the hdps parameter contains an offset that depends on the panel type. this offset is the constant in the equation to describes parameter t 14 min in the ac timing tables for the various panel types. 4 the vdp must be a minimum of 2 lines. 5 offset for stn and cstn panel = 22, offset for tft panel = 5. 10.4.1 generic stn panel timing hdp hdps 1pclk ht (= 1 line) vt (= 1 frame) vpw vps vdps vdp hps hpw lframe lline mod (lden) ldata[17:0] lline mod (lden) ldata[17:0] lshift
ssd1905 rev 1.3 10/2002 solomon 83 figure 10-13 : generic stn panel timing vt = vertical total = [(reg[19h]bits1-0,reg[18h]bits7-0)+ 1] lines vps = lframe pulse start position = [(reg[27h] bits 1-0, reg[26h] bits 7-0)] x ht + (reg[31h] bits 1-0, reg[30h] bits 7-0) pixels vpw = lframe pulse width = [(reg[24h] bits 2-0) + 1] x ht + (reg[35h] bits 1-0, reg[34h] bits 7-0) ? (reg[31h] bits 1-0, reg[30h] bits 7-0) pixels vdps = vertical display period start position = [(reg[1fh]bits1-0,reg[1eh]bits7-0)] lines vdp = vertical display period = [(reg[1dh] bits 1-0, reg[1ch] bits 7-0) + 1] lines * the vdp must be a minimum of 2 lines ht = horizontal total = [((reg[12h] bits 6-0) + 1) x 8] pixels hps = lline pulse start position = [(reg[23h] bits 1-0, reg[22h] bits 7-0) + 1] pixels hpw = lline pulse width = [(reg[20h] bits 6-0) + 1] pixels hdps = horizontal display period start position = [(reg[17h]bits1-0,reg[16h]bits7-0)+ 22] pixels hdp = horizontal display period = [((reg[14h] bits 6-0) + 1) x 8] pixels ? the hdp must be a minimum of 32 pixels and can be increased by multiples of 8. *panel type bits (reg[10h] bits 1-0) = 00b (stn) *lframe pulse polarity bit (reg[24h] bit 7) = 1 (active high) *lline polarity bit (reg[20h] bit 7) = 1 (active high).
solomon rev 1.3 10/2002 ssd1905 84 10.4.2 monochrome 4-bit panel timing lden (mod) line239 line2 line1 line240 line3 line2 line1 1-320 1-319 1-318 1-317 1-8 1-7 1-6 1-4 1-3 1-2 1-5 1-1 lframe lline ldata [ 7:4 ] lline lshift lden (mod) ldata7 ldata6 ldata5 ldata4 vdp vndp hdp hndp *diagram drawn with 2 lline vertical blank period example timing for a 320x240 panel figure 10-14 : monochrome 4-bit panel timing vdp = vertical display period = (reg[1dh] bits 1:0, reg[1ch] bits 7:0) + 1 lines vndp = vertical non-display period = vt -vdp = (reg[19h] bits 1:0, reg[18h] bits 7:0) - (reg[1dh] bits 1:0, reg[1ch] bits 7:0) lines hdp = horizontal display period = ((reg[14h] bits 6:0) + 1) x 8ts hndp = horizontal non-display period = ht - hdp = (((reg[12h] bits 6:0) + 1) x 8ts) - (((reg[14h] bits 6:0) + 1) x 8ts)
ssd1905 rev 1.3 10/2002 solomon 85 t 14 t 13 t 12 t 11 t 10 t 9 t 8 t 7 t 6 t 5 t 4 t 3 sync timing data timing lframe lline lden (mod) lline lshift ldata[7:4] t 1 t 2 1 2 figure 10-15 : monochrome 4-bit panel a.c. timing
solomon rev 1.3 10/2002 ssd1905 86 table 10-15 : monochrome 4-bit panel a.c. timing symbol parameter min typ max units t 1 lframe setup to lline falling edge note 2 ts (note 1) t 2 lframe hold from lline falling edge note 3 ts t 3 lline period note 4 ts t 4 lline pulse width note 5 ts t 5 mod transition to lline falling edge note 6 ts t 6 lshift falling edge to lline rising edge note 7 ts t 7 lshift falling edge to lline falling edge t 6 + t 4 ts t 8 lline falling edge to lshift falling edge t 14 + 2 ts t 9 lshift period 4 ts t 10 lshift pulse width low 2 ts t 11 lshift pulse width high 2 ts t 12 ldata[7:4] setup to lshift falling edge 2 ts t 13 ldata[7:4] hold from lshift falling edge 2 ts t 14 lline falling edge to lshift rising edge note 8 ts 1. ts = pixel clock period 2. t 1 min = (hps+ hpw) ? (reg[31h] bits 1-0, reg[30h] bits 7-0) 3. t 2 min = vpw - t 1 min 4. t 3 min = ht 5. t 4 min = hpw 6. t 5 min = ht - hps 7. t 6 min = hps - (hdp + hdps - 2) if negative add t 3 min 8. t 14 min = hdps - (hps + t 4 min ) if negative add t 3 min
ssd1905 rev 1.3 10/2002 solomon 87 10.4.3 monochrome 8-bit panel timing lden (mod) line479 line2 line1 line480 line3 line2 line1 1-640 1-639 1-638 1-637 1-636 1-635 1-634 1-633 1-16 1-15 1-14 1-13 1-12 1-11 1-10 1-8 1-6 1-7 1-5 1-4 1-3 1-2 1-9 1-1 lframe lline ldata [ 7:0 ] lline lshift lden (mod) ldata7 ldata6 ldata5 ldata3 ldata4 ldata2 ldata1 ldata0 vdp vndp hdp hndp *diagram drawn with 2 lline vertical blank period example timing for a 640x480 panel figure 10-16 : monochrome 8-bit panel timing vdp = vertical display period = (reg[1dh] bits 1:0, reg[1ch] bits 7:0) + 1 lines vndp = vertical non-display period = vt-vdp = (reg[19h] bits 1:0, reg[18h] bits 7:0) - (reg[1dh] bits 1:0, reg[1ch] bits 7:0) lines hdp = horizontal display period = ((reg[14h] bits 6:0) + 1) x 8ts hndp = horizontal non-display period = ht - hdp = (((reg[12h] bits 6:0) + 1) x 8ts) - (((reg[14h] bits 6:0) + 1) x 8ts)
solomon rev 1.3 10/2002 ssd1905 88 t 14 t 13 t 12 t 11 t 10 t 9 t 8 t 7 t 6 t 5 t 4 t 3 sync timing data timing lframe lline lden (mod) lline lshift ldata[7:0] t 1 t 2 1 2 figure 10-17 : monochrome 8-bit panel a.c. timing
ssd1905 rev 1.3 10/2002 solomon 89 table 10-16 : monochrome 8-bit panel a.c. timing symbol parameter min typ max units t 1 lframe setup to lline falling edge note 2 ts (note 1) t 2 lframe hold from lline falling edge note 3 ts t 3 lline period note 4 ts t 4 lline pulse width note 5 ts t 5 mod transition to lline falling edge note 6 ts t 6 lshift falling edge to lline rising edge note 7 ts t 7 lshift falling edge to lline falling edge t 6 + t 4 ts t 8 lline falling edge to lshift falling edge t 14 + 4 ts t 9 lshift period 8 ts t 10 lshift pulse width low 4 ts t 11 lshift pulse width high 4 ts t 12 ldata[7:0] setup to lshift falling edge 4 ts t 13 ldata[7:0] hold from lshift falling edge 4 ts t 14 lline falling edge to lshift rising edge note 8 ts 1. ts = pixel clock period 2. t 1 min = (hps+ hpw) ? (reg[31h] bits 1-0, reg[30h] bits 7-0) 3. t 2 min = vpw - t 1 min 4. t 3 min = ht 5. t 4 min = hpw 6. t 5 min = ht - hps 7. t 6 min = hps - (hdp + hdps - 4) if negative add t 3 min 8. t 14 min = hdps - (hps + t 4 min ) if negative add t 3 min
solomon rev 1.3 10/2002 ssd1905 90 10.4.4 color 4-bit panel timing 1-b4 1-g4 1-r4 1-b3 lden (mod) line239 line2 line1 line240 line3 line2 line1 1-b320 1-g320 1-r320 1-b319 1-g3 1-r3 1-b2 1-r2 1-b1 1-g1 1-g2 1-r1 lframe lline ldata[7:4] lline lshift lden (mod) ldata7 ldata6 ldata5 ldata4 vdp vndp hdp hndp *diagram drawn with 2 lline vertical blank period example timing for a 320x240 panel figure 10-18 : color 4-bit panel timing vdp = vertical display period = (reg[1dh] bits 1:0, reg[1ch] bits 7:0) + 1 lines vndp = vertical non-display period = vt-vdp = (reg[19h] bits 1:0, reg[18h] bits 7:0) - (reg[1dh] bits 1:0, reg[1ch] bits 7:0) lines hdp = horizontal display period = ((reg[14h] bits 6:0) + 1) x 8ts hndp = horizontal non-display period = ht - hdp (((reg[12h] bits 6:0) + 1) x 8ts) - (((reg[14h] bits 6:0) + 1) x 8ts)
ssd1905 rev 1.3 10/2002 solomon 91 t 14 t 13 t 12 t 11 t 10 t 9 t 8 t 7 t 6 t 5 t 4 t 3 sync timing data timing lframe lline lden (mod) lline lshift ldata[7:4] t 1 t 2 1 2 figure 10-19 : color 4-bit panel a.c. timing
solomon rev 1.3 10/2002 ssd1905 92 table 10-17 : color 4-bit panel a.c. timing symbol parameter min typ max units t 1 lframe setup to lline falling edge note 2 ts (note 1) t 2 lframe hold from lline falling edge note 3 ts t 3 lline period note 4 ts t 4 lline pulse width note 5 ts t 5 mod transition to lline falling edge note 6 ts t 6 lshift falling edge to lline rising edge note 7 ts t 7 lshift falling edge to lline falling edge t 6 + t 4 ts t 8 lline falling edge to lshift falling edge t 14 + 0.5 ts t 9 lshift period 2 ts t 10 lshift pulse width low 1 ts t 11 lshift pulse width high 1 ts t 12 ldata[7:4] setup to lshift falling edge 1 ts t 13 ldata[7:4] hold from lshift falling edge 1 ts t 14 lline falling edge to lshift rising edge note 8 ts 1. ts = pixel clock period 2. t 1 min = (hps+ hpw) ? (reg[31h] bits 1-0, reg[30h] bits 7-0) 3. t 2 min = vpw - t 1 min 4. t 3 min = ht 5. t 4 min = hpw 6. t 5 min = ht - hps 7. t 6 min = hps - (hdp + hdps - 3) if negative add t 3 min 8. t 14 min = hdps - (hps + t 4 min ) + 1 if negative add t 3 min
ssd1905 rev 1.3 10/2002 solomon 93 10.4.5 color 8-bit panel timing (format stripe) 1-g7 1-r7 1-b6 1-g6 lden (mod) line479 line2 line1 line480 line3 line2 line1 1-g639 1-r639 1-b638 1-g638 1-b4 1-g4 1-r4 1-r2 1-b1 1-g1 1-b3 1-r1 lframe lline ldata[7:0] lline lshift lden (mod) ldata7 ldata6 ldata5 ldata4 vdp vndp hdp hndp *diagram drawn with 2 lline vertical blank period example timing for a 640x480 panel 1-b8 1-g8 1-r8 1-b7 1-b640 1-g640 1-r640 1-b639 1-r6 1-b5 1-g5 1-g3 1-r3 1-b2 1-r5 1-g2 ldata3 ldata2 ldata1 ldata0 figure 10-20 : color 8-bit panel timing (format stripe)
solomon rev 1.3 10/2002 ssd1905 94 vdp = vertical display period = (reg[1dh] bits 1:0, reg[1ch] bits 7:0) + 1 lines vndp = vertical non-display period = vt-vdp = (reg[19h] bits 1:0, reg[18h] bits 7:0) - (reg[1dh] bits 1:0, reg[1ch] bits 7:0) lines hdp = horizontal display period = ((reg[14h] bits 6:0) + 1) x 8ts hndp = horizontal non-display period = ht - hdp = (((reg[12h] bits 6:0) + 1) x 8ts) - (((reg[14h] bits 6:0) + 1) x 8ts) t 5 t 4 t 3 sync timing data timing lframe lline lline t 1 t 2 lden (mod) t 14 t 13 t 12 t 11 t 10 t 9 t 8 t 7 t 6 lshift ldata[7:0] 1 2 figure 10-21 : color 8-bit panel a.c. timing (format stripe)
ssd1905 rev 1.3 10/2002 solomon 95 table 10-18 : color 8-bit panel a.c. timing (format stripe) symbol parameter min typ max units t 1 lframe setup to lline falling edge note 2 ts (note 1) t 2 lframe hold from lline falling edge note 3 ts t 3 lline period note 4 ts t 4 lline pulse width note 5 ts t 5 mod transition to lline falling edge note 6 ts t 6 lshift falling edge to lline rising edge note 7 ts t 7 lshift falling edge to lline falling edge t 6 + t 4 ts t 8 lline falling edge to lshift falling edge t 14 + 2 ts t 9 lshift period 2 ts t 10 lshift pulse width low 1 ts t 11 lshift pulse width high 1 ts t 12 ldata[7:0] setup to lshift falling edge 1 ts t 13 ldata[7:0] hold to lshift falling edge 1 ts t 14 lline falling edge to lshift rising edge note 8 ts 1. ts = pixel clock period 2. t 1 min = (hps+ hpw) ? (reg[31h] bits 1-0, reg[30h] bits 7-0) 3. t 2 min = vpw - t 1 min 4. t 3 min = ht 5. t 4 min = hpw 6. t 5 min = t 3 min -hps 7. t 6 min = hps - (hdp + hdps - 1) if negative add t 3 min 8. t 14 min = hdps - (hps + t 4 min ) if negative add t 3 min
solomon rev 1.3 10/2002 ssd1905 96 10.4.6 generic tft panel timing lden hdp hdps hps ht (= 1 line) vt (= 1 frame) vpw vps vdps vdp hpw lframe lline lden ldata[17:0] lline ldata[17:0] lshift figure 10-22 : generic tft panel timing vt = vertical total = [(reg[19h] bits 1-0, reg[18h] bits 7-0) + 1] lines vps = lframe pulse start position = [(reg[27h] bits 1-0, reg[26h] bits 7-0)] x ht + (reg[31h] bits 1-0, reg[30h] bits 7-0) pixels vpw = lframe pulse width = [(reg[24h]bits2-0)+ 1] x ht + (reg[35h] bits 1-0, reg[34h] bits 7-0) ? (reg[31h] bits 1-0, reg[30h] bits 7-0) pixels
ssd1905 rev 1.3 10/2002 solomon 97 vdps = vertical display period start position = [(reg[1fh]bits1-0,reg[1eh]bits7-0)] lines vdp = vertical display period = [(reg[1dh]bits1-0,reg[1ch]bits7-0)+ 1] lines * the vdp must be a minimum of 2 lines ht = horizontal total = [((reg[12h] bits 6-0) + 1) x 8] pixels hps = lline pulse start position = [(reg[23h] bits 1-0, reg[22h] bits 7-0) + 1] pixels hpw = lline pulse width = [(reg[20h] bits 6-0)+ 1] pixels hdps = horizontal display period start position = [(reg[17h] bits 1-0, reg[16h] bits 7-0) + 5] pixels hdp = horizontal display period = [((reg[14h] bits 6-0) + 1) x 8] pixels ? the hdp must be a minimum of 32 pixels and can be increased by multiples of 8. *panel type bits (reg[10h] bits 1-0) = 01 (tft) *lline pulse polarity bit (reg[24h] bit 7) = 0 (active low) *lframe polarity bit (reg[20h] bit 7) = 0 (active low) 10.4.7 9/12/18-bit tft panel timing hndp 1 ldata[11:0] 1-1 line480 1-640 lframe line1 lline line480 lden lline lshift lden ldata[11:0] hdp hndp 2 vndp 2 vdp vndp 1 note: lden is used to indicated the first pixel example timing for 12-bit 640x480 panel 1-2 figure 10-23 : 12-bit tft panel timing
solomon rev 1.3 10/2002 ssd1905 98 vdp = vertical display period = vdp lines vndp = vertical non-display period = vndp1 + vndp2 = vt ? vdp lines vndp1 = vertical non-display period 1 = vndp - vndp2 lines vndp2 = vertical non-display period 2 = vdps - vps lines if negative add vt hdp = horizontal display period = hdp ts hndp = horizontal non-display period = hndp1 + hndp2 = ht - hdp ts hndp1 = horizontal non-display period 1 = hdps ? hps ts if negative add ht hndp2 = horizontal non-display period 2 = hps - hdp + hdps ts if negative add ht
ssd1905 rev 1.3 10/2002 solomon 99 t 6 t 10 t 5 lshift lframe lline lline lden ldata[11:0] t 9 t 11 t 10 t 12 t 1 t 2 t 3 t 4 t 8 t 16 t 15 t 13 t 14 2 639 640 1 t 7 figure 10-24 : tft a.c. timing
solomon rev 1.3 10/2002 ssd1905 100 table 10-19 : tft a.c. timing symbol parameter min typ max units t 1 lframe cycle time vt lines t 2 lframe pulse width low vpw lines t 3 lframe falling edge to lline falling edge phase difference hps + 1 ts(note1) t 4 lline cycle time ht ts t 5 lline pulse width low hpw ts t 6 lline falling edge to lden active note 2 250 ts t 7 lden pulse width hdp ts t 8 lden falling edge to lline falling edge note 3 ts t 9 lshift period 1 ts t 10 lshift pulse width high 0.5 ts t 11 lshift pulse width low 0.5 ts t 12 lline setup to lshift falling edge 0.5 ts t 13 lden to lshift falling edge setup time 0.5 ts t 14 lden hold from lshift falling edge 0.5 ts t 15 data setup to lshift falling edge 0.5 ts t 16 data hold from lshift falling edge 0.5 ts 1. ts = pixel clock period 2. t 6 min = hdps - hps if negative add ht 3. t 8 min = hps - (hdp + hdps ) if negative add ht
ssd1905 rev 1.3 10/2002 solomon 101 10.4.8 160x160 sharp hr-tft panel timing (e.g. lq031b1ddxx) t 5 t 10 t 6 t 9 t 7 t 12 ldata[17:0] d160 t 3 gpio3 (spl) lframe (sps) lline (lp) lshift (clk) gpio1 (cls) t 13 t 1 t 2 t 4 t 8 d1 d2 d3 lline (lp) gpio0 (ps) gpio2 (rev) t 11 figure 10-25 : 160x160 sharp hr-tft panel horizontal timing
solomon rev 1.3 10/2002 ssd1905 102 table 10-20 : 160x160 sharp hr-tft horizontal timing symbol parameter min typ max units t 1 lline start position 13 ts (note 1) t 2 horizontal total period 180 ts t 3 lline width 2 ts t 4 lshift period 1 ts t 5 data setup to lshift rising edge 0.5 ts t 6 data hold from lshift rising edge 0.5 ts t 7 horizontal display start position 5 ts t 8 horizontal display period 160 ts t 9 lline rising edge to gpio3 rising edge 4 ts t 10 gpio3 pulse width 1 ts t 11 gpio1(gpio0) pulse width 136 ts t 12 gpio1 rising edge (gpio0 falling edge) to lline rise edge 4 ts t 13 gpio2 toggle edge to lline rise edge 10 ts 1. ts = pixel clock period 2. t 1 typ = (reg[22h] bits 7-0) + 1 3. t 2 typ = ((reg[12h] bits 6-0) + 1) x 8 4. t 3 typ = (reg[20h] bits 6-0) + 1 5. t 7 typ = ((reg[16h] bits 7-0) + 1) - ((reg[22h] bits 7-0) + 1) 6. t 8 typ = ((reg[14h] bits 6-0) + 1) x 8
ssd1905 rev 1.3 10/2002 solomon 103 t 4 t 12 t 3 t 2 line1 line160 t 10 lline (lp) lshift (clk) ldata[17:0] lframe (sps) gpio1(cls) reg[38h] bit 0 = 0 t 9 t 11 gpio0(ps) reg[38h] bit 1 = 1 line2 t 1 t 14 t 13 t 6 t 7 t 8 gpio1(cls) reg[38h] bit 0 = 0 gpio0(ps) reg[38h] bit 1 = 0 gpio1(cls) reg[38h] bit 0 = 1 gpio0(ps) reg[38h] bit 1 = 1 t 5 figure 10-26 : 160x160 sharp hr-tft panel vertical timing
solomon rev 1.3 10/2002 ssd1905 104 table 10-21 : 160x160 sharp hr-tft panel vertical timing symbol parameter min typ max units t 1 vertical total period 203 lines t 2 vertical display start position 40 lines t 3 vertical display period 160 lines t 4 lframe sync pulse width 2 lines t 5 1 lframe falling edge to gpio1 alternate timing start 5 lines t 6 1 gpio1 alternate timing period 4 lines t 7 2 lframe falling edge to gpio0 alternate timing start 40 lines t 8 2 gpio0 alternate timing period 162 lines t 9 gpio1 first pulse rising edge to lline rising edge 4 ts (note 1) t 10 1 gpio1 first pulse width 48 ts t 11 1 gpio1 first pulse falling edge to second pulse rising edge 40 ts t 12 1 gpio1 second pulse width 48 ts t 13 2 gpio0 falling edge to lline rising edge 4 ts t 14 2 gpio0 low pulse width 24 ts 1. ts = pixel clock period 1 timing for cls signal change bit enabled (reg[38h] bit 0 = 0) only 2 timing for ps signal change bit enabled (reg[38h] bit 1 = 1) only
ssd1905 rev 1.3 10/2002 solomon 105 10.4.9 320x240 sharp hr-tft panel timing (e.g. lq039q2ds01) t 11 t 10 t 9 t 6 t 12 ldata[17:0] d320 t 3 t 5 gpio3 (spl) lframe (sps) lline (lp) lshift (clk) gpio1 (cls) t 13 t 1 t 2 t 4 t 8 d1 d2 d3 lline (lp) gpio0 (ps) gpio2 (rev) t 7 figure 10-27 : 320x240 sharp hr-tft panel horizontal timing
solomon rev 1.3 10/2002 ssd1905 106 table 10-22 : 320x240 sharp hr-tft panel horizontal timing symbol parameter min typ max units t 1 lline start position 14 ts (note 1) t 2 horizontal total period 400 440 ts t 3 lline width 1 ts t 4 lshift period 1 ts t 5 data setup to lshift rising edge 0.5 ts t 6 data hold from lshift rising edge 0.5 ts t 7 horizontal display start position 60 ts t 8 horizontal display period 320 ts t 9 lline rising edge to gpio3 rising edge 59 ts t 10 gpio3 pulse width 1 ts t 11 gpio1(gpio0) pulse width 353 ts t 12 gpio1 rising edge (gpio0 falling edge) to lline rise edge 5 ts t 13 gpio2 toggle edge to lline rise edge 11 ts 1. ts = pixel clock period 2. t 1 typ = (reg[22h] bits 7-0) + 1 3. t 2 typ = ((reg[12h] bits 6-0) + 1) x 8 4. t 3 typ = (reg[20h] bits 6-0) + 1 5. t 7 typ = ((reg[16h] bits 7-0) + 1) - ((reg[22h] bits 7-0) + 1) 6. t 8 typ = ((reg[14h] bits 6-0) + 1) x 8 t 4 t 3 t 2 line1 line240 ldata[17:0] lframe (sps) line2 t 1 figure 10-28 : 320x240 sharp hr-tft panel vertical timing table 10-23 : 320x240 sharp hr-tft panel vertical timing symbol parameter min typ max units t 1 vertical total period 245 330 lines t 2 vertical display start position 4 lines t 3 vertical display period 240 lines t 4 vertical sync pulse width 2 lines
ssd1905 rev 1.3 10/2002 solomon 107 11 clocks the following diagram provides a block diagram of the ssd1905 internal clocks. clki mclk pclk1 pwmclk1 clk mux clki-gen bclk mclk pwmclk2 pclk2 pclk pwmclk stop control clki auxclk stop control auxclk-gen figure 11-1 : clock generator block diagram 11.1 clock descriptions 11.1.1 bclk bclk is an internal clock derived from clki. bclk can be a divided version ( 1, 2, 3, 4) of clki. clki is typically derived from the host cpu bus clock. the source clock options for bclk may be selected as in the following table. table 11-1 : bclk clock selection source clock options bclk selection clki cf[7:6] = 00 clki 2 cf[7:6] = 01 clki 3 cf[7:6] = 10 clki 4 cf[7:6] = 11
solomon rev 1.3 10/2002 ssd1905 108 note for synchronous bus interfaces, it is recommended that bclk be set the same as the cpu bus clock (not a divided version of clki) e.g. sh-3, sh-4. 11.1.2 mclk mclk provides the internal clock required to access the embedded sram. the ssd1905 is designed with efficient power saving control for clocks (clocks are turned off when not used). furthermore, reducing the mclk frequency relative to the bclk frequency increases the cpu cycle latency and so reduces screen update performance. for a balance of power saving and performance, the mclk should be configured to have a high enough frequency setting to provide sufficient screen refresh as well as acceptable cpu cycle latency. the source clock options for mclk may be selected as in the following table. table 11-2 : mclk clock selection source clock options mclk selection (reg[04h] bits 5:4) bclk 00 bclk 2 01 bclk 3 10 bclk 4 11 11.1.3 pclk pclk is the internal clock used to control the lcd panel. pclk should be chosen to match the optimum frame rate of the lcd panel. see section 13 ?frame rate calculation? for details on the relationship between pclk and frame rate. some flexibility is possible in the selection of pclk. firstly, lcd panels typically have a range of permissible frame rates. secondly, it may be possible to choose a higher pclk frequency and tailor the horizontal and vertical non- display periods to lower the frame-rate to its optimal value. the source clock options for pclk may be selected as in the following table. table 11-3 : pclk clock selection source clock options pclk selection ( reg[05h] bits 6:4) mclk 00h mclk 2 10h mclk 3 20h mclk 4 30h mclk 8 40h bclk 01h bclk 2 11h bclk 3 21h bclk 4 31h bclk 8 41h clki 02h clki 2 12h clki 3 22h clki 4 32h clki 8 42h auxclk 03h auxclk 2 13h auxclk 3 23h auxclk 4 33h
ssd1905 rev 1.3 10/2002 solomon 109 auxclk 8 43h there is a relationship between the frequency of mclk and pclk that must be maintained, see table 11-4 : relationship between mclk and pclk. table 11-4 : relationship between mclk and pclk color depth (bpp) mclk to pclk relationship 16 f mclk f pclk x 2 8 f mclk f pclk 4 f mclk f pclk 2 2 f mclk f pclk 4 1 f mclk f pclk 8 11.1.4 pwmclk pwmclk is the internal clock used by the pulse width modulator for output to the panel. the source clock options for pwmclk may be selected as in the following table. for further information on controlling pwmclk, see section 7.2.9 ?pulse width modulation (pwm) clock and contrast voltage (cv) pulse configuration registers?. note the ssd1905 provides pulse width modulation output on the pin lpwmout. lpwmout can be used to control lcd panels which support pwm control of the back-light inverter. table 11-5 : pwmclk clock selection source clock options pwmclk selection reg[b1h] bit 0 clki 0 auxclk 1 11.2 clocks versus functions table 11-6 : ssd1905 internal clock requirements, lists the internal clocks required for the following ssd1905 functions. table 11-6 : ssd1905 internal clock requirements function bus clock (bclk) memory clock (mclk) pixel clock (pclk) pwm clock (pwmclk) register read/write required not required not required not required memory read/write required required not required not required look-up table register read/write required not required not required not required software power saving required not required not required not required lcd output required required required not required pwm / cv output required required required required
solomon rev 1.3 10/2002 ssd1905 110 12 power saving mode power saving mode is incorporated into the ssd1905 to accommodate the need for power reduction in the hand- held device market. this mode is enabled via the power saving mode enable bit (reg[a0h] bit 0). power saving mode power down the panel and stop display refresh accesses to the display buffer. table 12-1 : power saving mode function summary software power saving normal io access possible? yes yes memory access possible? no 1 yes look-up table registers access possible? yes yes sequence controller running? no yes display active? no yes lcd interface outputs forced low 4 active pwmclk stopped active gpio3:0 pins configured for hr-tft 2 forced low active gpio pins configured as gpios access possible ? 2 yes 3 yes note : 1 when power saving mode is enabled, the memory controlled is powered down. the status of the memory controlled is indicated by the memory controller power saving status bit (reg[a0h] bit 3). for power saving status ac timing, see section 10.3.3 ?power saving status?. 2 gpio pins are configured using the configurations pin cf3 which is latched on the rising edge of reset#. for information on cf3, see table 5-6 : summary of power-on/reset options. 3 gpios can be accessed and if configured as outputs can be changed. 4 except the lcd interface pins lden and lshift in stn and cstn mode. after reset, the ssd1905 stays in power saving mode. software must initialize the chip (i.e. programs all registers) and then clear the power saving mode enable bit. 13 frame rate calculation the following formula is used to calculate the display frame rate. ) ( ) ( vt x ht f framerate pclk = where: f pclk = pclk frequency (hz) ht = horizontal total = ((reg[12h] bits 6-0) + 1) x 8 ts vt = vertical total = ((reg[19h] bits 1-0, reg[18h] bits 7-0) + 1) lines
ssd1905 rev 1.3 10/2002 solomon 111 14 display data formats the following diagrams show the display mode data formats. 1 bpp: byte 1 byte 2 host address bit 7 bit 0 a 1 a 6 a 0 a 2 a 3 a 4 a 5 a 7 a 9 a 14 a 8 a 10 a 11 a 12 a 13 a 15 a 17 a 22 a 16 a 18 a 19 a 20 a 21 a 23 lut p 0 p 1 p 2 p 3 p 4 p 5 p 6 p 7 p n = rgb value from lut index (a n ) panel display display buffer 2 bpp: byte 0 byte 1 byte 2 host address bit 7 bit 0 b 0 a 3 a 0 a 1 b 1 a 2 b 2 b 3 b 4 a 7 a 4 a 5 b 5 a 6 b 6 b 7 b 8 a 11 a 8 a 9 b 9 a 10 b 10 b 11 lut p 0 p 1 p 2 p 3 p 4 p 5 p 6 p 7 p n = rgb value from lut index (a n , b n ) panel display display buffer 4 bpp: byte 0 byte 1 byte 2 host address bit 7 bit 0 b 0 c 1 a 0 c 0 d 0 a 1 b 1 d 1 b 4 c 5 a 4 c 4 d 4 a 5 b 5 d 5 lut p 0 p 1 p 2 p 3 p 4 p 5 p 6 p 7 p n = rgb value from lut index (a n , b n , c n , d n ) panel display display buffer 8 bpp: bit 7 bit 0 byte 0 byte 1 byte 2 host address b 0 g 0 a 0 c 0 d 0 e 0 f 0 h 0 b 1 g 1 a 1 c 1 d 1 e 1 f 1 h 1 b 2 g 2 a 2 c 2 d 2 e 2 f 2 h 2 lut p 0 p 1 p 2 p 3 p 4 p 5 p 6 p 7 p n = rgb value from lut index (a n , b n , c n , d n , e n , f n , g n , h n ) panel display display buffer b 2 c 3 a 2 c 2 d 2 a 3 b 3 d 3 byte 0 16 bpp: p 0 p 1 p 2 p 3 p 4 p 5 p 6 p 7 panel display g 0 1 b 0 1 g 0 0 b 0 4 b 0 3 b 0 2 b 0 0 g 1 1 b 1 1 g 1 0 b 1 4 b 1 3 b 1 2 b 1 0 r 0 3 g 0 4 r 0 2 r 0 1 r 0 0 g 0 5 g 0 3 r 1 3 g 1 4 r 1 2 r 1 1 r 1 0 g 1 5 g 1 3 g 0 2 r 0 4 g 1 2 r 1 4 bypasses lut byte 0 byte 1 byte 2 byte 3 host address display buffer p n = (r n 4 - 0 , g n 5 - 0 , b n 4 - 0 ) bit 7 bit 0 figure 14-1 : 1/2/4/8/16 bit-per-pixel display data memory organization note 1. for 16 bpp format, rn, gn, bn represent the red, green, and blue color components.
solomon rev 1.3 10/2002 ssd1905 112 15 look-up table architecture the following figures are intended to show the display data output path only. note when color invert is enabled the display color is inverted after the look-up table. 15.1 monochrome modes the green look-up table (lut) is used for all monochrome modes. 15.1.1 1 bit-per-pixel monochrome mode 1 bit-per-pixel data from display buffer 6-bit gray data green look-up table 256x6 00 01 figure 15-1 : 1 bit-per-pixel monochrome mode data output path 15.1.2 2 bit-per-pixel monochrome mode 2 bit-per-pixel data from display buffer 6-bit gray data green look-up table 256x6 00 01 02 03 figure 15-2 : 2 bit-per-pixel monochrome mode data output path
ssd1905 rev 1.3 10/2002 solomon 113 15.1.3 4 bit-per-pixel monochrome mode 4 bit-per-pixel data from display buffer 6-bit gray data green look-up table 256x6 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f figure 15-3 : 4 bit-per-pixel monochrome mode data output path 15.1.4 8 bit-per-pixel monochrome mode 8 bit-per-pixel data from display buffer 00 01 02 03 04 05 06 07 f8 f9 fa fb fc fd fe ff 6-bit gray data green look-up table 256x6 figure 15-4 : 8 bit-per-pixel monochrome mode data output path 15.1.5 16 bit-per-pixel monochrome mode the lut is bypassed and the green data is directly mapped for this color depth? see figure 14-1 : 1/2/4/8/16 bit-per-pixel display data memory organization.
solomon rev 1.3 10/2002 ssd1905 114 15.2 color modes 15.2.1 1 bit-per-pixel color 1 bit-per-pixel data from display buffer 00 01 6-bit red data red look-up table 256x6 6-bit green data green look-up table 256x6 6-bit blue data blue look-up table 256x6 00 01 00 01 figure 15-5 : 1 bit-per-pixel color mode data output path
ssd1905 rev 1.3 10/2002 solomon 115 15.2.2 2 bit-per-pixel color 2 bit-per-pixel data from display buffer 00 01 02 03 6-bit red data red look-up table 256x6 6-bit green data green look-up table 256x6 6-bit blue data blue look-up table 256x6 00 01 02 03 00 01 02 03 figure 15-6 : 2 bit-per-pixel color mode data output path
solomon rev 1.3 10/2002 ssd1905 116 15.2.3 4 bit-per-pixel color 4 bit-per-pixel data from display buffer 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 6-bit red data red look-up table 256x6 6-bit green data green look-up table 256x6 6-bit blue data blue look-up table 256x6 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f figure 15-7 : 4 bit-per-pixel color mode data output path
ssd1905 rev 1.3 10/2002 solomon 117 15.2.4 8 bit-per-pixel color mode 8 bit-per-pixel data from display buffer 00 01 02 03 04 05 06 07 f8 f9 fa fb fc fd fe ff 6-bit red data red look-up table 256x6 00 01 02 03 04 05 06 07 f8 f9 fa fb fc fd fe ff 6-bit green data green look-up table 256x6 00 01 02 03 04 05 06 07 f8 f9 fa fb fc fd fe ff 6-bit blue data blue look-up table 256x6 figure 15-8 : 8 bit-per-pixel color mode data output path
solomon rev 1.3 10/2002 ssd1905 118 15.2.5 16 bit-per-pixel color mode the lut is bypassed at 16 bpp and the color data is directly mapped for this color depth. the color pixel is arranged as 5-6-5 rgb format. see figure 14-1 : 1/2/4/8/16 bit-per-pixel display data memory organization. 16 big-endian bus interface 16.1 byte swapping bus data the display buffer and register architecture of the ssd1905 is inherently little-endian. if configured as big- endian (cf4 = 1 at reset), bus accesses are automatically handled by byte swapping all read/write data to/from the internal display buffer and registers. bus data byte swapping translates all byte accesses correctly to the ssd1905 register and display buffer locations. to maintain the correct translation for 16-bit word access, even address bytes must be mapped to the msb of the 16-bit word, and odd address bytes to the lsb of the 16-bit word. for example: aa cc dd bb bb dd cc aa aabb ccdd msb lsb 2 0 2 0 0 15 0 15 display data byte swap system memory address display buffer address d[15:8] d[7:0] * msb is assumed to be associated with even address. * lsb is assumed to be associated with odd address. display buffer (little-endian) system memory (big-endian) cpu data byte swap byte write 11h to register address 1eh -> reg[1eh] <= 11h byte write 22h to register address 1fh -> reg[1fh] <= 22h word write 1122h to register address 1eh-> reg[1eh] <= 11h reg[1fh] <= 22h figure 16-1 : byte-swapping for 16 bpp
ssd1905 rev 1.3 10/2002 solomon 119 16.1.1 16 bpp color depth for 16 bpp color depth, the display data byte swap bit (reg[71h] bit 6) must be set to 1 for 16 bpp color depth, the msb of the 16-bit pixel data is stored at the even system memory address location and the lsb of the 16-bit pixel data is stored at the odd system memory address location. bus data byte swapping (automatic when the ssd1905 is configured for big-endian) causes the 16-bit pixel data to be stored byte-swapped in the ssd1905 display buffer. during display refresh this stored data must be byte-swapped again before it is sent to the display. 16.1.2 1/2/4/8 bpp color depth for 1/2/4/8 bpp color depth, byte swapping must be performed on the bus data but not the display data. for 1/2/4/8 bpp color depth, the display data byte swap bit (reg[71h] bit 6) must be set to 0. 11 22 22 11 11 22 0 0 0 15 0 15 system memory address display buffer address d[15:8] d[7:0] * high byte lane (d[15:8]) data (e.g. 11) is associated with even address. * low byte lane (d[7:0]) data (e.g. 22) is associated with odd address. display buffer (little-endian) system memory (big-endian) cpu data byte swap figure 16-2 : byte-swapping for 1/2/4/8 bpp
solomon rev 1.3 10/2002 ssd1905 120 17 virtual display mode virtual display refers to the situation where the image to be viewed is larger than the physical display. the difference can be in the horizontal, vertical or both dimensions. to view the image, the display is used as a window into the display buffer. at any given time only a portion of the image is visible. panning and scrolling are used to view the full image. panning describes the horizontal (side to side) motion of the display area. scrolling describes the vertical (up and down) motion of the display area. the main window display start address register specifies the starting address of main window image in the display buffer. the main window line address offset register determines the number of horizontal pixels in the virtual image. figure 17-1 : main window inside virtual image area illustrates the situation. 320 x 240 virtual image area 240 x 160 main window panning scrolling figure 17-1 : main window inside virtual image area
ssd1905 rev 1.3 10/2002 solomon 121 18 display rotate mode most computer displays are refreshed in landscape orientation ? from left to right and top to bottom. computer images are stored in the same manner. display rotate mode is designed to rotate the displayed image on an lcd by 90 , 180 , or 270 in an counter-clockwise direction. the rotation is done in hardware and is transparent to the user for all display buffer reads and writes. by processing the rotation in hardware, display rotate mode offers a performance advantage over software rotation of the displayed image. the image is not actually rotated in the display buffer since there is no address translation during cpu read/write. the image is rotated during display refresh. 18.1 90 display rotate mode the following figure shows how the programmer sees a 160x240 rotated image and how the image is being displayed. the application image is written to the ssd1905 in the following sense: a?b?c?d. the display is refreshed by the ssd1905 in the following sense: b-d-a-c. a b c d display rotate window 160 240 a b c d display rotate window 240 160 display start address (panel origin) physical memory start address image seen by programmer = image in display buffer image refreshed by ssd1905 figure 18-1 : relationship between the screen image and the image refreshed in 90 display rotate mode. 18.1.1 register programming enable 90 display rotate mode set display rotate mode select bits to 01 (reg[71h] bits 1:0 = 01). display start address the display refresh circuitry starts at pixel ?b?, therefore the main window display start address registers (reg[74h], reg[75h], reg[76h]) must be programmed with the address of pixel ?b?. to calculate the value of the address of pixel ?b? use the following formula (assumes 8bpp color depth). main window display start address bits 16-0 = ((image address + (panel height x bpp 8)) 4) ?1 = ((0 + (160 pixels x 8 bpp 8)) 4) ? 1 = 39 (27h)
solomon rev 1.3 10/2002 ssd1905 122 line address offset the main window line address offset register (reg[78h], reg[79h]) is based on the display width and programmed using the following formula. main window line address offset bits 9-0 = display width in pixels (32 bpp) = 160 pixels (32 8 bpp) = 40 (28h) 18.2 180 display rotate mode the following figure shows how the programmer sees a 240x160 landscape image and how the image is being displayed. the application image is written to the ssd1905 in the following sense: a?b?c?d. the display is refreshed by the ssd1905 in the following sense: d-c-b-a. a b c d display rotate window physical memory start address image seen by programmer = image in display buffer 160 240 240 160 display start address (panel origin) image refreshed by ssd1905 display rotate window ab cd figure 18-2 : relationship between the screen image and the image refreshed in 180 display rotate mode. 18.2.1 register programming enable 180 display rotate mode set display rotate mode select bits to 10 (reg[71h] bits 1:0 = 10). display start address the display refresh circuitry starts at pixel ?d?, therefore the main window display start address registers (reg[74h], reg[75h], reg[76h]) must be programmed with the address of pixel ?d?. to calculate the value of the address of pixel ?d? use the following formula (assumes 8bpp color depth). main window display start address bits 16-0 = ((image address + (image width x (panel height ? 1) + panel width) x bpp 8) 4) ?1 = ((0 + (240 pixels x 159 pixels + 240 pixels) x 8 bpp 8) 4) ? 1 = 9599 (257fh)
ssd1905 rev 1.3 10/2002 solomon 123 line address offset the main window line address offset register (reg[78h], reg[79h]) is based on the display width and programmed using the following formula. main window line address offset bits 9-0 = display width in pixels (32 bpp) = 240 pixels (32 8 bpp) = 60 (3ch) 18.3 270 display rotate mode the following figure shows how the programmer sees a 160x240 rotated image and how the image is being displayed. the application image is written to the ssd1905 in the following sense: a?b?c?d. the display is refreshed by the ssd1905 in the following sense: c-a-d-b. a b c d display rotate window 160 240 d c b a display rotate window 240 160 display start address (panel origin) physical memory start address image seen by programmer = image in display buffer image refreshed by ssd1905 figure 18-3 : relationship between the screen image and the image refreshed in 270 display rotate mode. 18.3.1 register programming enable 270 display rotate mode set display rotate mode select bits to 11 (reg[71h] bits 1:0 = 11). display start address the display refresh circuitry starts at pixel ?c?, therefore the main window display start address registers (reg[74h], reg[75h], reg[76h]) must be programmed with the address of pixel ?c?. to calculate the value of the address of pixel ?c? use the following formula (assumes 8bpp color depth). main window display start address bits 16-0 = (image address + ((panel width ? 1) x image width x bpp 8) 4) = (0 + ((240 pixels ? 1) x 160 pixels x 8 bpp 8) 4) = 9560 (2558h)
solomon rev 1.3 10/2002 ssd1905 124 line address offset the main window line address offset register (reg[78h], reg[79h]) is based on the display width and programmed using the following formula. main window line address offset bits 9-0 = display width in pixels (32 bpp) = 160 pixels (32 8 bpp) = 40 (28h) 19 floating window mode this mode enables a floating window within the main display window. the floating window can be positioned anywhere within the virtual display and is controlled through the floating window control registers (reg[7ch] through reg[91h]). the floating window retains the same color depth and display orientation as the main window. the following diagram shows an example of a floating window within a main window and the registers used to position it. normal orientation mode floating window start y position (reg[89h],reg[88h]) floating window main window floating window end y position (reg[91h],reg[90h]) floating window end x position (reg[8dh],reg[8ch]) panel?s origin floating window start x position (reg[85h],reg[84h]) figure 19-1 : floating window with display rotate mode disabled
ssd1905 rev 1.3 10/2002 solomon 125 19.1 with display rotate mode enabled 19.1.1 display rotate mode 90 90 display rotate mode floating window start y position (reg[89h],reg[88h]) floating window main window floating window end y position (reg[91h],reg[90h]) floating window start x position (reg[85h],reg[84h]) floating window end x position (reg[8dh],reg[8ch]) panel?s origin figure 19-2 : floating window with display rotate mode 90 enabled 19.1.2 display rotate mode 180 180 display rotate mode floating window main window floating window start x position (reg[85h],reg[84h]) floating window end x position (reg[8dh],reg[8ch]) panel?s origin floating window start y position (reg[89h],reg[88h]) floating window end y position (reg[91h],reg[90h]) figure 19-3 : floating window with display rotate mode 180 enabled
solomon rev 1.3 10/2002 ssd1905 126 19.1.3 display rotate mode 270 270 display rotate mode floating window start y position (reg[89h],reg[88h]) floating window main window floating window end y position (reg[91h],reg[90h]) floating window start x position (reg[85h],reg[84h]) floating window end x position (reg[8dh],reg[8ch]) panel?s origin figure 19-4 : floating window with display rotate mode 270 enabled
ssd1905 rev 1.3 10/2002 solomon 127 20 hardware cursor mode this mode enables two cursors on the main display window. the cursors can be positioned anywhere within the display and are controlled through cursor mode registers (reg[c0h] through reg[111h]). cursor support is available only at 4/8/16-bpp display modes. each cursor pixel is 2-bit and the indexing scheme is as follows: table 20-1 : indexing scheme for hardware cursor value color of cursor 1 / cursor 2 00 transparent 01 content of color index 1 register (reg[e1h], reg[e0h] / reg[109h], reg[108h]) 10 content of color index 2 register (reg[e5h], reg[e4h] / reg[10dh], reg[10ch]) 11 content of color index 3 register (reg[e9h], reg[e8h] / reg[111h], reg[110h]) three 16-bit color index registers (reg[e0h] through reg[111h]) have been implemented for each cursor. only the lower portion of the color index register is used in 4/8-bpp display modes. the lut is bypassed and the color data is directly mapped for 16-bpp display mode. 4 bit-per-pixel 15 12 11 8 7 4 3 0 don?t care 4-bit color index 8 bit-per-pixel 15 12 11 8 7 4 3 0 don?t care 8-bit color index 16 bit-per-pixel (the index registers represents the 16-bit color component) 15 13 12 8 7 3 2 0 green component bits 2-0 blue component bits 4-0 red component bits 4-0 green component bits 5-3 the display precedence is cursor1 > cursor2 > floating window > main window. main window floating window cursor 1 cursor 2 figure 20-1 : display precedence in hardware cursor note : the maximum size for cursor is 32x32 pixels, while the minimum size varies for different color depths and display orientations.
solomon rev 1.3 10/2002 ssd1905 128 the cursors retains the same color depth and display orientation as the main window. the following diagram shows an example of two cursors within a main window and the registers used to position it. cursor1 main-window cursor1 position x (reg[d1h],reg[d0h]) panel?s origin cursor1 position y (reg[d5h],reg[d4h]) cursor2 cursor2 position y (reg[fdh],reg[fch]) cursor2 position x (reg[f9h],reg[f8h]) figure 20-2 : cursors on the main window 20.1 with display rotate mode enabled 20.1.1 display rotate mode 90 cursor1 main-window cursor1 position x (reg[d1h],reg[d0h]) panel?s origin cursor1 position y (reg[d5h],reg[d4h]) cursor2 cursor2 position y (reg[fdh],reg[fch]) cursor2 position x (reg[f9h],reg[f8h]) figure 20-3 : cursors with display rotate mode 90 enabled
ssd1905 rev 1.3 10/2002 solomon 129 20.1.2 display rotate mode 180 cursor1 main-window cursor1 position x (reg[d1h],reg[d0h]) panel?s origin cursor1 position y (reg[d5h],reg[d4h]) cursor2 cursor2 position y (reg[fdh],reg[fch]) cursor2 position x (reg[f9h],reg[f8h]) figure 20-4 : cursors with display rotate mode 180 enabled 20.1.3 display rotate mode 270 cursor1 main-window cursor1 position x (reg[d1h],reg[d0h]) panel?s origin cursor1 position y (reg[d5h],reg[d4h]) cursor2 cursor2 position y (reg[fdh],reg[fch]) cursor2 position x (reg[f9h],reg[f8h]) figure 20-5 : cursors with display rotate mode 270 enabled 20.2 pixel format (normal orientation mode) assume the pixel data stores start at address n, which n must be divisible by 4 (i.e. aligned to 32-bit boundary). in this example, a 16x16 cursor is displayed which each cursor index is defined by x and y coordinate, c(y,x).
solomon rev 1.3 10/2002 ssd1905 130 20.2.1 4/8/16 bit-per-pixel 7 6 5 4 3 2 1 0 addr. n c(0,0) c(0,1) c(0,2) c(0,3) addr. n + 1 c(0,4) c(0,5) c(0,6) c(0,7) addr. n + 2 c(0,8) c(0,9) c(0,10) c(0,11) addr. n + 3 c(0,12) c(0,13) c(0,14) c(0,15) addr. n + 4 c(1,0) c(1,1) c(1,2) c(1,3) . . . addr. n + 60 c(15,0) c(15,1) c(15,2) c(15,3) addr. n + 61 c(15,4) c(15,5) c(15,6) c(15,7) addr. n + 62 c(15,8) c(15,9) c(15,10) c(15,11) addr. n + 63 c(15,12) c(15,13) c(15,14) c(15,15) 20.3 pixel format (90 ? display rotate mode) assume the pixel data stores start at address n, which n must be divisible by 4 (i.e. aligned to 32-bit boundary). in this example, a 16x16 cursor is displayed which each cursor index is defined x and y coordinate, c(y,x). 20.3.1 4 bit-per-pixel 7 6 5 4 3 2 1 0 addr. n c(0,8) c(0,9) c(0,10) c(0,11) addr. n + 1 c(0,12) c(0,13) c(0,14) c(0,15) addr. n + 2 c(1,8) c(1,9) c(1,10) c(1,11) addr. n + 3 c(1,12) c(1,13) c(1,14) c(1,15) . . . addr. n + 28 c(14,8) c(14,9) c(14,10) c(14,11) addr. n + 29 c(14,12) c(14,13) c(14,14) c(14,15) addr. n + 30 c(15,8) c(15,9) c(15,10) c(15,11) addr. n + 31 c(15,12) c(15,13) c(15,14) c(15,15) addr. n + 32 c(0,0) c(0,1) c(0,2) c(0,3) addr. n + 33 c(0,4) c(0,5) c(0,6) c(0,7) addr. n + 34 c(1,0) c(1,1) c(1,2) c(1,3) addr. n + 35 c(1,4) c(1,5) c(1,6) c(1,7) . . . addr. n + 60 c(14,0) c(14,1) c(14,2) c(14,3) addr. n + 61 c(14,4) c(14,5) c(14,6) c(14,7) addr. n + 62 c(15,0) c(15,1) c(15,2) c(15,3) addr. n + 63 c(15,4) c(15,5) c(15,6) c(15,7)
ssd1905 rev 1.3 10/2002 solomon 131 20.3.2 8 bit-per-pixel 7 6 5 4 3 2 1 0 addr. n c(0,12) c(0,13) c(0,14) c(0,15) addr. n + 1 c(1,12) c(1,13) c(1,14) c(1,15) addr. n + 2 c(2,12) c(2,13) c(2,14) c(2,15) addr. n + 3 c(3,12) c(3,13) c(3,14) c(3,15) . . . addr. n + 12 c(12,12) c(12,13) c(12,14) c(12,15) addr. n + 13 c(13,12) c(13,13) c(13,14) c(13,15) addr. n + 14 c(14,12) c(14,13) c(14,14) c(14,15) addr. n + 15 c(15,12) c(15,13) c(15,14) c(15,15) addr. n + 16 c(0,8) c(0,9) c(0,10) c(0,11) addr. n + 17 c(1,8) c(1,9) c(1,10) c(1,11) addr. n + 18 c(2,8) c(2,9) c(2,10) c(2,11) addr. n + 19 c(3,8) c(3,9) c(3,10) c(3,11) . . . addr. n + 60 c(12,0) c(12,1) c(12,2) c(12,3) addr. n + 61 c(13,0) c(13,1) c(13,2) c(13,3) addr. n + 62 c(14,0) c(14,1) c(14,2) c(14,3) addr. n + 63 c(15,0) c(15,1) c(15,2) c(15,3) 20.3.3 16 bit-per-pixel 7 6 5 4 3 2 1 0 addr. n c(0,14) c(0,15) c(1,14) c(1,15) addr. n + 1 c(2,14) c(2,15) c(3,14) c(3,15) addr. n + 2 c(4,14) c(4,15) c(5,14) c(5,15) addr. n + 3 c(6,14) c(6,15) c(7,14) c(7,15) addr. n + 4 c(8,14) c(8,15) c(9,14) c(9,15) addr. n + 5 c(10,14) c(10,15) c(11,14) c(11,15) addr. n + 6 c(12,14) c(12,15) c(12,14) c(12,15) addr. n + 7 c(14,14) c(14,15) c(15,14) c(15,15) addr. n + 8 c(0,12) c(0,13) c(1,12) c(1,13) addr. n + 9 c(2,12) c(2,13) c(3,12) c(3,13) addr. n + 10 c(4,12) c(4,13) c(5,12) c(5,13) addr. n + 11 c(6,12) c(6,13) c(7,12) c(7,13) . . . addr. n + 60 c(8,0) c(8,1) c(9,0) c(9,1) addr. n + 61 c(10,0) c(10,1) c(11,0) c(11,1) addr. n + 62 c(12,0) c(12,1) c(12,0) c(12,1) addr. n + 63 c(14,0) c(14,1) c(15,0) c(15,1)
solomon rev 1.3 10/2002 ssd1905 132 20.4 pixel format (180 ? display rotate mode) assume the pixel data stores start at address n, which n must be divisible by 4 (i.e. aligned to 32-bit boundary). in this example, a 16x16 cursor is displayed which each cursor index is defined by x and y coordinate, c(y,x). 20.4.1 4 bit-per-pixel 7 6 5 4 3 2 1 0 addr. n c(15,8) c(15,9) c(15,10) c(15,11) addr. n + 1 c(15,12) c(15,13) c(15,14) c(15,15) addr. n + 2 c(15,0) c(15,1) c(15,2) c(15,3) addr. n + 3 c(15,4) c(15,5) c(15,6) c(15,7) addr. n + 4 c(14,8) c(14,9) c(14,10) c(14,11) . . . addr. n + 60 c(0,8) c(0,9) c(0,10) c(0,11) addr. n + 61 c(0,12) c(0,13) c(0,14) c(0,15) addr. n + 62 c(0,0) c(0,1) c(0,2) c(0,3) addr. n + 63 c(0,4) c(0,5) c(0,6) c(0,7) 20.4.2 8 bit-per-pixel 7 6 5 4 3 2 1 0 addr. n c(15,12) c(15,13) c(15,14) c(15,15) addr. n + 1 c(15,8) c(15,9) c(15,10) c(15,11) addr. n + 2 c(15,4) c(15,5) c(15,6) c(15,7) addr. n + 3 c(15,0) c(15,1) c(15,2) c(15,3) addr. n + 4 c(14,12) c(14,13) c(14,14) c(14,15) . . . addr. n + 60 c(0,12) c(0,13) c(0,14) c(0,15) addr. n + 61 c(0,8) c(0,9) c(0,10) c(0,11) addr. n + 62 c(0,4) c(0,5) c(0,6) c(0,7) addr. n + 63 c(0,0) c(0,1) c(0,2) c(0,3)
ssd1905 rev 1.3 10/2002 solomon 133 20.4.3 16 bit-per-pixel 7 6 5 4 3 2 1 0 addr. n c(15,14) c(15,15) c(15,12) c(15,13) addr. n + 1 c(15,10) c(15,11) c(15,8) c(15,9) addr. n + 2 c(15,6) c(15,7) c(15,4) c(15,5) addr. n + 3 c(15,2) c(15,3) c(15,0) c(15,1) addr. n + 4 c(14,14) c(14,15) c(14,12) c(14,13) . . . addr. n + 60 c(0,14) c(0,15) c(0,12) c(0,13) addr. n + 61 c(0,10) c(0,11) c(0,8) c(0,9) addr. n + 62 c(0,6) c(0,7) c(0,4) c(0,5) addr. n + 63 c(0,2) c(0,3) c(0,0) c(0,1) 20.5 pixel format (270 ? display rotate mode) assume the pixel data stores start at address n, which n must be divisible by 4 (i.e. aligned to 32-bit boundary). in this example, a 16x16 cursor is displayed which each cursor index is defined by x and y coordinate, c(y,x). 20.5.1 4 bit-per-pixel 7 6 5 4 3 2 1 0 addr. n c(15,0) c(15,1) c(15,2) c(15,3) addr. n + 1 c(15,4) c(15,5) c(15,6) c(15,7) addr. n + 2 c(14,0) c(14,1) c(14,2) c(14,3) addr. n + 3 c(14,4) c(14,5) c(14,6) c(14,7) . . . addr. n + 28 c(1,0) c(1,1) c(1,2) c(1,3) addr. n + 29 c(1,4) c(1,5) c(1,6) c(1,7) addr. n + 30 c(0,0) c(0,1) c(0,2) c(0,3) addr. n + 31 c(0,4) c(0,5) c(0,6) c(0,7) addr. n + 32 c(15,8) c(15,9) c(15,10) c(15,11) addr. n + 33 c(15,12) c(15,13) c(15,14) c(15,15) addr. n + 34 c(14,8) c(14,9) c(14,10) c(14,11) addr. n + 35 c(14,12) c(14,13) c(14,14) c(14,15) . . . addr. n + 60 c(1,8) c(1,9) c(1,10) c(1,11) addr. n + 61 c(1,12) c(1,13) c(1,14) c(1,15) addr. n + 62 c(0,8) c(0,9) c(0,10) c(0,11) addr. n + 63 c(0,12) c(0,13) c(0,14) c(0,15)
solomon rev 1.3 10/2002 ssd1905 134 20.5.2 8 bit-per-pixel 7 6 5 4 3 2 1 0 addr. n c(15,0) c(15,1) c(15,2) c(15,3) addr. n + 1 c(14,0) c(14,1) c(14,2) c(14,3) addr. n + 2 c(13,0) c(13,1) c(13,2) c(13,3) addr. n + 3 c(12,0) c(12,1) c(12,2) c(12,3) . . . addr. n + 12 c(3,0) c(3,1) c(3,2) c(3,3) addr. n + 13 c(2,0) c(2,1) c(2,2) c(2,3) addr. n + 14 c(1,0) c(1,1) c(1,2) c(1,3) addr. n + 15 c(0,0) c(0,1) c(0,2) c(0,3) addr. n + 16 c(15,4) c(15,5) c(15,6) c(15,7) addr. n + 17 c(14,4) c(14,5) c(14,6) c(14,7) addr. n + 18 c(13,4) c(13,5) c(13,6) c(13,7) addr. n + 19 c(12,4) c(12,5) c(12,6) c(12,7) . . . addr. n + 60 c(3,12) c(3,13) c(3,14) c(3,15) addr. n + 61 c(2,12) c(2,13) c(2,14) c(2,15) addr. n + 62 c(1,12) c(1,13) c(1,14) c(1,15) addr. n + 63 c(0,12) c(0,13) c(0,14) c(0,15) 20.5.3 16 bit-per-pixel 7 6 5 4 3 2 1 0 addr. n c(15,0) c(15,1) c(14,0) c(14,1) addr. n + 1 c(13,0) c(13,1) c(12,0) c(12,1) addr. n + 2 c(11,0) c(11,1) c(10,0) c(10,1) addr. n + 3 c(9,0) c(9,1) c(8,0) c(8,1) addr. n + 4 c(7,0) c(7,1) c(6,0) c(6,1) addr. n + 5 c(5,0) c(5,1) c(4,0) c(4,1) addr. n + 6 c(3,0) c(3,1) c(2,0) c(2,1) addr. n + 7 c(1,0) c(1,1) c(0,0) c(0,1) addr. n + 8 c(15,2) c(15,3) c(14,2) c(14,3) addr. n + 9 c(13,2) c(13,3) c(12,2) c(12,3) addr. n + 10 c(11,2) c(11,3) c(10,2) c(10,3) addr. n + 11 c(9,2) c(9,3) c(8,2) c(8,3) . . . addr. n + 60 c(7,14) c(7,15) c(6,14) c(6,15) addr. n + 61 c(5,14) c(5,15) c(4,14) c(4,15) addr. n + 62 c(3,14) c(3,15) c(2,14) c(2,15) addr. n + 63 c(1,14) c(1,15) c(0,14) c(0,15)
ssd1905 rev 1.3 10/2002 solomon 135 21 application examples auxcl k cf0 cf1 cf0 cf2 bias power 8-bit cstn lcd display d[7:0] lframe lline lshift mod corevdd iovdd ldata[7:0] lframe lline lshift lden gpo bs# m/r# cs# a [16:1] d[15:0] we0# we1# rd0# rd/wr# wait# clki reset# a 0 generic #1 bus a[27:17] csn# a[16:1] d[15:0] we0# we1# rd0# rd1# wait# buscl k reset# oscillator decoder ssd1905 3.3v 0.1 f iovdd 10k ? 4.7k ? 0.1 ? 10k ? 10k ? figure 21-1: typical system diagram (generic #1 bus)
solomon rev 1.3 10/2002 ssd1905 136 auxcl k cf0 cf1 cf0 cf2 bias powe r 9-bit tft display d[8:0] lframe lline lshift lden corevdd iovdd ldata[8:0] lframe lline lshift lden gpo bs# rd/wr# m/r# cs# a [16:0] d[15:0] we0# we1# rd# wait# clki reset# generic #2 bus a[27:17] csn# a[16:0] d[15:0] we# bhe# rd# wait# buscl k reset# oscillator decoder ssd1905 3.3v 0.1 f 0.1 ? 10k ? 0.1 ? 4.7k ? 4.7k ? figure 21-2 : typical system diagram (generic #2 bus)
ssd1905 rev 1.3 10/2002 solomon 137 auxcl k cf0 cf1 cf0 cf2 bias powe r 18-bit hr-tft display d[17:0] sps lp clk ps cls rev spl corevdd iovdd ldata[17:0] lframe lline lshift gpio0 gpio1 gpio2 gpio3 gpo rd# we0# m/r# cs# a [16:1] d[15:0] a 0 we1# bs# rd/wr# wait# clki reset# mc68k #1 bus a[23:17], fc0, fc1 a[16:1] d[15:0] lds# uds# as# r/w# dtack# cl k reset# oscillator 3.3v ssd1905 decoder decoder 0.1 ? 10k ? 0.1 ? 4.7k ? 4.7k ? figure 21-3 : typical system diagram (mc68k # 1, motorola 16-bit 68000)
solomon rev 1.3 10/2002 ssd1905 138 auxcl k cf0 cf1 cf0 cf2 cf5 bias powe r 12-bit tft display d[11:0] lshift lframe lline lden corevdd iovdd ldata[11:0] lshift lframe lline lden gpo bs# rd/wr# m/r# cs# a [16:1] d[15:0] we0# we1# rd # wait# clki reset# a 0 mc68ez328/ mc68vz328 dragonball bus a[25:17] csx# a[16:1] d[15:0] lwe# uwe# oe# dtack# clko reset# oscillator ssd1905 decoder 3.3v 0.1 f 0.1 ? 10k ? 4.7k ? 0.1 ? 4.7k ? 10k ? 10k ? figure 21-4 : typical system diagram (motorola mc68ez328/mc68vz328 ?dragonball? bus)
ssd1905 rev 1.3 10/2002 solomon 139 auxcl k cf0 cf1 cf0 cf2 cf5 bias power 12-bit tft display d[11:0] lframe lline lshift lden corevdd iovdd ldata[11:0] lframe lline lshift lden gpo m/r# cs# a [16:1] d[15:0] we0# we1# bs# rd/wr# rd# wait# clki reset# a 0 sh-3 bus a[25:17] csn# a[16:1] d[15:0] we0# we1# bs# rd/wr# rd# wait# ckio reset# oscillator decoder 3.3v ssd1905 4.7k ? 4.7k ? 4.7k ? 4.7k ? 4.7k ? figure 21-5 : typical system diagram (hitachi sh-3 bus)
solomon rev 1.3 10/2002 ssd1905 140 auxcl k cf0 cf1 cf0 cf2 cf5 bias powe r 18-bit tft display d[17:0] lframe lline lshift lden corevdd iovdd ldata[17:0] lframe lline lshift lden gpo m/r# cs# a [16:1] d[15:0] we0# we1# bs# rd/wr# rd# wait# clki reset# a 0 sh-4 bus a[25:17] csn# a[16:1] d[15:0] we0# we1# bs# rd/wr# rd# rdy# ckio reset# oscillator decoder 3.3v ssd1905 4.7k ? 4.7k ? 4.7k ? iovdd 10k ? 4.7k ? figure 21-6 : typical system diagram (hitachi sh-4 bus)
ssd1905 rev 1.3 10/2002 solomon 141 22 appendix 22.1 package mechanical drawing for 100 pins tqfp
solomon rev 1.3 10/2002 ssd1905 142 22.2 register table table 22-1 : ssd1905 register table (1 of 2) register pg register pg read-only configuration registers floating window registers reg[01h] display buffer size register 15 reg[7ch] floating window display start address register 0 36 reg[02h] configuration readback register 15 reg[7dh] floating window display start address register 1 36 reg[03h] product / revision code register 16 reg[7eh] floating window display start address register 2 36 clock configuration registers reg[80h] floating window line address offset register 0 37 reg[04h] memory clock configuration register 16 reg[81h] floating window line address offset register 1 37 reg[05h] pixel clock configuration register 16 reg[84h] floating window start position x register 0 37 look-up table registers reg[85h] floating window start position x register 1 38 reg[08h] look-up table blue write data register 17 reg[88h] floating window start position y register 0 38 reg[09h] look-up table green write data register 18 reg[89h] floating window start position y register 1 39 reg[0ah] look-up table red write data register 18 reg[8ch] floating window end position x register 0 39 reg[0bh] look-up table write address register 19 reg[8dh] floating window end position x register 1 40 reg[0ch] look-up table blue read data register 19 reg[90h] floating window end position y register 0 40 reg[0dh] look-up table green read data register 19 reg[91h] floating window end position y register 1 41 reg[0eh] look-up table red read data register 20 miscellaneous registers reg[0fh] look-up table read address register 20 reg[a0h] power saving configuration register 41 panel configuration registers reg[a2h] software reset register 42 reg[10h] panel type register 21 reg[a4h] scratch pad register 0 42 reg[11h] mod rate register 22 reg[a5h] scratch pad register 1 42 reg[12h] horizontal total register 22 general purpose io pins registers reg[14h] horizontal display period register 23 reg[a8h] general purpose io pins configuration register 0 43 reg[16h] horizontal display period start position register 0 23 reg[a9h] general purpose io pins configuration register 1 44 reg[17h] horizontal display period start position register 1 23 reg[ach] general purpose io pins status/control register 0 44 reg[18h] vertical total register 0 23 reg[adh] general purpose io pins status/control register 1 45 reg[19h] vertical total register 1 24 pwm clock and cv pulse configuration registers reg[1ch] vertical display period register 0 24 reg[b0h] pwm clock / cv pulse control register 46 reg[1dh] vertical display period register 1 24 reg[b1h] pwm clock / cv pulse configuration register 47 reg[1eh] vertical display period start position register 0 25 reg[b2h] cv pulse burst length register 48 reg[1fh] vertical display period start position register 1 25 reg[b3h] pwm duty cycle register 48 reg[20h] lline pulse width register 25 reg[22h] lline pulse start position register 0 26 reg[23h] lline pulse start position register 1 26 reg[24h] lframe pulse width register 26 reg[26h] lframe pulse start position register 0 27 reg[27h] lframe pulse start position register 1 27 reg[30h] lframe pulse start offset register 0 27 reg[31h] lframe pulse start offset register 1 27 reg[34h] lframe pulse stop offset register 0 28 reg[35h] lframe pulse stop offset register 1 28 reg[38h] hr-tft special output register 28 reg[3ch] gpio0 pulse start register 29 reg[3eh] gpio0 pulse stop register 29 reg[40h] gpio2 pulse delay register 30 reg[45h] stn color depth control register 30 reg[50h] dynamic dithering control register 31 display mode registers reg[70h] display mode register 31 reg[71h] special effects register 33 reg[74h] main window display start address register 0 34 reg[75h] main window display start address register 1 34 reg[76h] main window display start address register 2 35 reg[78h] main window line address offset register 0 35 reg[79h] main window line address offset register 1 35
ssd1905 rev 1.3 10/2002 solomon 143 table 22-2 : ssd1905 register table (2 of 2) register pg cursor mode registers reg[c0h] cursor feature register 49 reg[c4h] cursor1 blink total register 0 49 reg[c5h] cursor1 blink total register 1 49 reg[c8h] cursor1 blink on register 0 50 reg[c9h] cursor1 blink on register 1 50 reg[cch] cursor1 memory start register 0 50 reg[cdh] cursor1 memory start register 1 50 reg[ceh] cursor1 memory start register 2 50 reg[d0h] cursor1 position x register 0 51 reg[d1h] cursor1 position x register 1 51 reg[d4h] cursor1 position y register 0 51 reg[d5h] cursor1 position y register 1 51 reg[d8h] cursor1 horizontal size register 52 reg[dch] cursor1 vertical size register 52 reg[e0h] cursor1 color index1 register 0 53 reg[e1h] cursor1 color index1 register 1 53 reg[e4h] cursor1 color index2 register 0 53 reg[e5h] cursor1 color index2 register 1 54 reg[e8h] cursor1 color index3 register 0 54 reg[e9h] cursor1 color index3 register 1 54 reg[ech] cursor2 blink total register 0 54 reg[edh] cursor2 blink total register 1 55 reg[f0h] cursor2 blink on register 0 55 reg[f1h] cursor2 blink on register 1 55 reg[f4h] cursor2 memory start register 0 55 reg[f5h] cursor2 memory start register 1 56 reg[f6h] cursor2 memory start register 2 56 reg[f8h] cursor2 position x register 0 56 reg[f9h] cursor2 position x register 1 56 reg[fch] cursor2 position y register 0 56 reg[fdh] cursor2 position y register 1 57 reg[100h] cursor2 horizontal size register 57 reg[104h] cursor2 vertical size register 57 reg[108h] cursor2 color index1 register 0 58 reg[109h] cursor2 color index1 register 1 58 reg[10ch] cursor2 color index2 register 0 58 reg[10dh] cursor2 color index2 register 1 58 reg[110h] cursor2 color index3 register 0 59 reg[111h] cursor2 color index3 register 1 59
solomon rev 1.3 10/2002 ssd1905 144 solomon systech reserves the right to make changes without further notice to any products herein. solomon systech makes no warr anty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does solomon systech assu me any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without li mitation consequential or incidental damages. ?typical? parameters can and do vary in different applications. all operating parameters, including ?typica ls? must be validated for each customer application by customer?s technical experts. solomon systech does not convey any license under its patent rights nor the rights of others. solomon systech products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the solom on systech product could create a situation where personal injury or death may occur. should buyer purchase or use solomon systech products for any suc h unintended or unauthorized application, buyer shall indemnify and hold solomon systech and its offices, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any clai m of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that solomon systech was negligent regard ing the design or manufacture of the part.

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